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A low-power analog spike detector for extracellular neural recordings 用于细胞外神经记录的低功率模拟尖峰检测器
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399675
C.L. Rogers, J. Harris
{"title":"A low-power analog spike detector for extracellular neural recordings","authors":"C.L. Rogers, J. Harris","doi":"10.1109/ICECS.2004.1399675","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399675","url":null,"abstract":"This paper discusses a low-power spike detection circuit, which reduces bandwidth from neural recordings by only outputting a short pulse at each neural spike time. Communication bandwidth is dramatically reduced to the number of spikes. The principal idea is to use two low pass filters, one with a higher cutoff frequency to remove high frequency noise and the other with a lower cutoff frequency to create a local average. When the difference between the signal and the local average rises above a threshold, a spike is detected. The circuit uses subthreshold CMOS to keep the power consumption low enough for integration of many channels in an implanted device. This spike detection method shows promising results towards a robust and unsupervised algorithm that is lower power and more compact than existing spike detection methods.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"17 1","pages":"290-293"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80722642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
SOC modeling methodology for architectural exploration and software development 用于架构探索和软件开发的SOC建模方法
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399698
Michal Silbermintz, Amir Sahar, Itay Peled, M. Anschel, Emil Watralov, H. Miller, E. Weisberger
{"title":"SOC modeling methodology for architectural exploration and software development","authors":"Michal Silbermintz, Amir Sahar, Itay Peled, M. Anschel, Emil Watralov, H. Miller, E. Weisberger","doi":"10.1109/ICECS.2004.1399698","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399698","url":null,"abstract":"The paper introduces a system-on-chip (SOC) modeling methodology that enables the use of a single model for multiple purposes throughout a project's life cycle, starting from the architectural definition phase, continuing with the microarchitectural optimization and ending with the software development and optimization phase. These different purposes are served by enabling multiple approaches for modeling applications, providing capabilities for configuring and refining the hardware model and reaching a high accuracy level while maintaining a good simulation speed.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"1993 1","pages":"383-386"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82393053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
ISFET CMOS compatible design and encapsulation challenges ISFET CMOS兼容设计和封装挑战
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399736
L. Sudakov-Boreysha, A. Morgenshtein, U. Dinnar, Y. Nemirovsky
{"title":"ISFET CMOS compatible design and encapsulation challenges","authors":"L. Sudakov-Boreysha, A. Morgenshtein, U. Dinnar, Y. Nemirovsky","doi":"10.1109/ICECS.2004.1399736","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399736","url":null,"abstract":"This work presents the main challenges in ISFET encapsulation. It analyzes SU8 drawbacks as an encapsulant and presents a novel flip-chip bonding packaging concept.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"30 1","pages":"535-538"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89535711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Fuzzy decision diagram realization by analog CMOS summing amplifiers 用模拟CMOS和放大器实现模糊决策图
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399674
V. Varshavsky, I. Levin, V. Marakhovsky, A. Ruderman, N. Kravchenko
{"title":"Fuzzy decision diagram realization by analog CMOS summing amplifiers","authors":"V. Varshavsky, I. Levin, V. Marakhovsky, A. Ruderman, N. Kravchenko","doi":"10.1109/ICECS.2004.1399674","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399674","url":null,"abstract":"The functional completeness of a summing amplifier with saturation in an arbitrary value multi-valued logic, proven in previous works, gives a theoretical background for analog implementation of fuzzy devices. Practical design techniques for multi-valued analog fuzzy controllers still have to be developed. Compared with the traditional approach, analog CMOS fuzzy controller implementation has the advantages of higher speed, lower power consumption, smaller die area and more. This paper introduces some special design techniques and provides design examples for an industrial fuzzy controller implementation confirmed by SPICE simulations.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"173 1","pages":"286-289"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77495498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A jitter insensitive continuous-time /spl Sigma//spl Delta/ modulator using transmission lines 使用传输线的抖动不敏感连续时间/spl Sigma//spl Delta调制器
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399626
L. Hernández, P. Rombouts, E. Prefasi, S. Patón, Mario Garcia, C. Lopez
{"title":"A jitter insensitive continuous-time /spl Sigma//spl Delta/ modulator using transmission lines","authors":"L. Hernández, P. Rombouts, E. Prefasi, S. Patón, Mario Garcia, C. Lopez","doi":"10.1109/ICECS.2004.1399626","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399626","url":null,"abstract":"This work presents a prototype low pass continuous time sigma delta modulator which uses transmission lines in its loop filter rather than capacitive integrators. As has been shown in prior theoretical work, such a structure allows us to desensitize the modulator against clock jitter and excess loop delay. The prototype single-bit modulator was designed for an oversampling ratio of 128. Clocked at 53.7 MHz it achieves a peak SNR of 67 dB. In an experiment with an excessive clock jitter of 1% of the clock period, the SNDR is degraded by only 5dB compared to the case without jitter. This is 15dB better than an equivalent modulator with capacitive integrators.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"84 1","pages":"109-112"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79942561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Practical performance of planar spiral inductors 平面螺旋电感的实用性能
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399724
A. Telli, S. Demir, M. Askar
{"title":"Practical performance of planar spiral inductors","authors":"A. Telli, S. Demir, M. Askar","doi":"10.1109/ICECS.2004.1399724","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399724","url":null,"abstract":"Inductors are essential elements for RF design. For RFIC design, bondwires, planar solenoidal and planar spiral inductors are available. Due to some limitations of bondwires and planar solenoidal inductors, planar spiral inductors are the most popular ones. Designers try to get accurate lumped element models for planar spiral inductors in order to be able to simulate the circuit performance correctly before the integrated circuit is manufactured. Planar spiral inductor measurement methods are discussed, and the comparison between lumped element model simulation results and experimental measurement results are given. The results of this study show that it is possible to model planar spiral inductors with lumped element circuit models, parameters of which can be calculated by basic, but accurate, expressions.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"90 1","pages":"487-490"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87285668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Criterion of design for small value integrated self-inductors 小值集成自感器设计准则
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399725
G. Petit, R. Kielbasa, V. Petit
{"title":"Criterion of design for small value integrated self-inductors","authors":"G. Petit, R. Kielbasa, V. Petit","doi":"10.1109/ICECS.2004.1399725","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399725","url":null,"abstract":"Facing the increased frequencies used in analog products, integrated-circuit designers find that the X or upper band has its own problems, especially in the case of passive components. The paper focuses on inductor design and layout, opposing classical analog integrated inductors and hyper frequency lines. After studying separately each solution and pointing out their limits on an actual SOS (silicon on sapphire) 0.5 /spl mu/m case, a methodology to solve this issue is revealed and a chosen criterion is supplied.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"68 1","pages":"491-494"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73494385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis and design of a dual band reconfigurable VCO 双频可重构压控振荡器的分析与设计
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399608
A. Mazzanti, P. Uggetti, R. Battaglia, F. Svelto
{"title":"Analysis and design of a dual band reconfigurable VCO","authors":"A. Mazzanti, P. Uggetti, R. Battaglia, F. Svelto","doi":"10.1109/ICECS.2004.1399608","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399608","url":null,"abstract":"A systematic approach to the design of reconfigurable LC VCOs is proposed in this paper. The focus is on the choice of the reactive element of the tank most suited to switch the oscillation frequency. The optimum is the component that determines the tank Q. As an example, the design of a GSM900/1800 VCO in a 0.13 /spl mu/m CMOS technology, switching a series inductor, is discussed. At this frequency, the tank Q is roughly the inductor Q, and series inductor switching allows area savings with respect to parallel switching.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"35 1","pages":"37-40"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78336783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Input-free cascode V/sub thn/ and V/sub thp/ extractor circuits 无输入级联码V/sub thn/和V/sub thp/提取电路
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399673
Yanbin Wang, G. Tarr, Yanjie Wang
{"title":"Input-free cascode V/sub thn/ and V/sub thp/ extractor circuits","authors":"Yanbin Wang, G. Tarr, Yanjie Wang","doi":"10.1109/ICECS.2004.1399673","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399673","url":null,"abstract":"Input-free nMOS and pMOS V/sub th/ (threshold voltage) extractor circuits are presented. They use a cascode structure to eliminate the error caused by the body effect. The extracted V/sub th/ for nMOS and pMOS is referenced to ground and V/sub DD/ respectively. Both nMOS and pMOS V/sub th/ extractors have high accuracy of almost 100% from the HSPICE simulation. The nMOS and pMOS extractor circuits have been simulated in HSPICE using TSMC 0.35 /spl mu/m CMOS technology at 2 V and 2.9 V power supply with low power consumption of 0.29 mW and 0.44 mW respectively.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"44 1","pages":"282-285"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90852735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Investigation of on-chip PLL irregularities under stress conditions - case study 应力条件下片上锁相环不规则性的研究-案例研究
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399750
Y. Weizman, Y. Fefer, S. Sofer, E. Baruch
{"title":"Investigation of on-chip PLL irregularities under stress conditions - case study","authors":"Y. Weizman, Y. Fefer, S. Sofer, E. Baruch","doi":"10.1109/ICECS.2004.1399750","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399750","url":null,"abstract":"In modern high performance VLSI design, on-chip phase locked loop (PLL) performance degradation due to intensive core switching activities is becoming an influential factor. Under certain borderline conditions, the PLL may become unstable. The analysis herein describes PLL irregularities under marginal mode, frequency and voltage conditions combined with intensive core operations. After lengthy analysis that included step-by-step elimination of all noise sources, the cause of instability was explained by coupling between a voltage spike on core power supply line and the internal control signal of the voltage controlled oscillator of the PLL through the chip substrate. The solution to the problem was suggested by changing the PLL dynamic characteristics. Through this investigation we studied the noise crosstalk issue in mixed mode (analog and digital) systems and also the PLL dynamics under stress conditions, which demonstrates the complexity of PLL analysis in a system-on-chip environment.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"1 1","pages":"591-594"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90250412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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