2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN)最新文献_第4页

Design and implementation of PAL and PLA using reversible logic on FPGA SPARTAN 3E 用可逆逻辑在FPGA SPARTAN 3E上设计和实现PAL和PLA

2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN) Pub Date : 2017-03-01 DOI: 10.1109/ICSCN.2017.8085646

K. Anusudha, Gopi Chand Naguboina

{"title":"Design and implementation of PAL and PLA using reversible logic on FPGA SPARTAN 3E","authors":"K. Anusudha, Gopi Chand Naguboina","doi":"10.1109/ICSCN.2017.8085646","DOIUrl":"https://doi.org/10.1109/ICSCN.2017.8085646","url":null,"abstract":"Reversible logic is the emerging field for research in present era. The aim of this paper is to design and synthesize a Programmable array Logic (PAL) and Programmable Logic array (PLA) using reversible logic with minimum quantum cost. The PAL is a Programmable Logic device which consists of programmable AND Gates and fixed OR gates array. The PLA is the PLD which contains programmable AND array and programmable OR array. The PLDs are the combinational circuits mainly used to realize Boolean functions on our interest. An n input and k output Boolean function f (a1, a2, a3,…. an) (referred as (n, k)) is said to be logically reversible if and only if, the number of inputs are equal to the number of outputs i.e., ‘n’ equals ‘k’ and the input pattern maps uniquely maps the output pattern. The reversible logic must run both forward and backward in such a way that the inputs can also be retrieved from outputs. There are many reversible logic gates in literature like NOT gate, Feynman Gate (CNOT gate), Double Feynman Gate, Peres Gate, TR gate, Seynman Gate and many more. Fan-out and Feed-back are not allowed in Logical Reversibility. To overcome the Fan out limitation, the signals from required output lines are duplicated to desired lines using additional reversible combinational circuits. Reversible Logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI etc., Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption and low heat dissipation. In this paper, the design of PAL and PLA which has less heat dissipation and low power consumption is proposed. The designed circuits are analyzed in terms of quantum cost, garbage outputs and number of gates. The Circuit has been designed and simulated using Xilinx software and implemented on FPGA SPARTAN — 3E.","PeriodicalId":383458,"journal":{"name":"2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN)","volume":"42 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113981049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Analysis of WDM system using DCF 基于DCF的WDM系统分析

2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN) Pub Date : 2017-03-01 DOI: 10.1109/ICSCN.2017.8085726

J. Karunya, P. Prakash

引用次数: 5

Phishing websites classifier using polynomial neural networks in genetic algorithm 钓鱼网站分类器采用多项式神经网络中的遗传算法

2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN) Pub Date : 2017-03-01 DOI: 10.1109/ICSCN.2017.8085736

S. Gayathri

引用次数: 4

Design and simulation of low power, high gain and high bandwidth recycling folded cascode OTA 低功耗、高增益、高带宽回收折叠级联码OTA的设计与仿真

2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN) Pub Date : 2017-03-01 DOI: 10.1109/ICSCN.2017.8085720

T. V. Prasula, D. Meganathan

引用次数: 6

Analysis of sense amplifier circuits in nanometer technologies 纳米技术中感测放大电路的分析

2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN) Pub Date : 2017-03-01 DOI: 10.1109/ICSCN.2017.8085666

M. Suma, P. Madhumathy, S. B. Kumar

{"title":"Analysis of sense amplifier circuits in nanometer technologies","authors":"M. Suma, P. Madhumathy, S. B. Kumar","doi":"10.1109/ICSCN.2017.8085666","DOIUrl":"https://doi.org/10.1109/ICSCN.2017.8085666","url":null,"abstract":"The sense amplifier circuit is a very important part of the memory. It is used to access the stored data in bit cell during read cycle. Sense intensifier enhances the little distinction between bit lines to the full swing level. Its execution influences the get to time and power dissemination of memory and henceforth by lessening the detecting deferral and power utilization of sense speaker the execution of memory makes strides. Since the majority of the memory related operations are perused operations, this causes a vast sparing in the general power scattered by the memory. Additionally as sense intensifiers scatters extensive amount of short out power instead of the dynamic power disseminated by the cell exhibit, substantial power is spared. The requirement for the hearty outline of low power fast CMOS simple VLSI circuits is developing immensely. This development is because of the innovative drive that originates from the decrease of the base component size to downsize the chip zone. Downsizing the transistor size can then coordinate more circuit segments are solitary chip zone and bring down the cost. Likewise littler geometry normally brings down the parasitic capacitances, which implies higher working pace and lower control utilization. For a comparative analysis, we will be cataloguing the different sense amplifiers in use currently, using various nanometer technologies such as 180nm, 90nm and 45nm. We will then be providing an extensive comparison using these technologies in order to provide a clear picture about the best technology to be used. The comparison will provide information regarding various parameters such as sensing delay and power consumption.","PeriodicalId":383458,"journal":{"name":"2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116275483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Smart accident alert and toll pay system 智能事故警报和收费系统

2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN) Pub Date : 2017-03-01 DOI: 10.1109/ICSCN.2017.8085691

G. Shanmugasundaram, Archiot Anil, S. Deepak, Faizal Ahmed

引用次数: 4

Interpolation tool: Qualitative and quantitative analysis for machine vision applications 插值工具:用于机器视觉应用的定性和定量分析

2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN) Pub Date : 2017-03-01 DOI: 10.1109/ICSCN.2017.8085712

A. Karpagam, M. Manikandan

引用次数: 0

Computed tomography scan simulation techniques: A survey 计算机断层扫描模拟技术综述

2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN) Pub Date : 2017-03-01 DOI: 10.1109/ICSCN.2017.8085679

V. Venkatesan, M. Sandhya, B. M. Jenefer

引用次数: 3

An estimation theory-based approach for speech enhancement 基于估计理论的语音增强方法

2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN) Pub Date : 2017-03-01 DOI: 10.1109/ICSCN.2017.8085702

Mirishkar Sai Ganesh, M. Karthik, B. Patnaik

引用次数: 0

Blackout restoration process by PHEV charging station integrated system using virtual instrumentation 插电式混合动力充电站综合系统的停电恢复过程

2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN) Pub Date : 2017-03-01 DOI: 10.1109/ICSCN.2017.8085664

R. Hariharan, P. Rani

引用次数: 4