2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)最新文献_第2页

Lightweight resource estimation model to extend battery life in video playback 轻量级的资源估计模型，以延长电池寿命的视频播放

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) Pub Date : 2013-07-15 DOI: 10.1109/SAMOS.2013.6621111

Tero Rintaluoma, O. Silvén

引用次数: 0

PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration 用于mpsoc运行时重构的参数化和接口数据流元模型

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) Pub Date : 2013-07-15 DOI: 10.1109/SAMOS.2013.6621104

K. Desnos, M. Pelcat, J. Nezan, S. Bhattacharyya, Slaheddine Aridhi

引用次数: 87

An embedded hardware-efficient architecture for real-time cascade Support Vector Machine classification 一种用于实时级联支持向量机分类的嵌入式硬件高效架构

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) Pub Date : 2013-07-15 DOI: 10.1109/SAMOS.2013.6621115

C. Kyrkou, T. Theocharides, C. Bouganis

{"title":"An embedded hardware-efficient architecture for real-time cascade Support Vector Machine classification","authors":"C. Kyrkou, T. Theocharides, C. Bouganis","doi":"10.1109/SAMOS.2013.6621115","DOIUrl":"https://doi.org/10.1109/SAMOS.2013.6621115","url":null,"abstract":"Support Vector Machines (SVMs) are considered as a state-of-the-art classification algorithm yielding high accuracy rates. However, SVMs often require processing a large number of support vectors, making the classification process computationally demanding, especially when considering embedded applications. Cascade SVMs have been proposed in an attempt to speed-up classification times, but improved performance comes at a cost of additional hardware resources. Consequently, in this paper we propose an optimized architecture for cascaded SVM processing, along with a hardware reduction method in order to reduce the overheads from the implementation of additional stages in the cascade, leading to significant resource and power savings for embedded applications. The architecture was implemented on a Virtex 5 FPGA platform and evaluated using face detection as the target application on 640×480 resolution images. Additionally, it was compared against implementations of the same cascade processing architecture but without using the reduction method, and a single parallel SVM classifier. The proposed architecture achieves an average performance of 70 frames-per-second, demonstrating a speed-up of 5× over the single parallel SVM classifier. Furthermore, the hardware reduction method results in the utilization of 43% less hardware resources and a 20% reduction in power, with only 0.7% reduction in classification accuracy.","PeriodicalId":382307,"journal":{"name":"2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116295411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Stochastic modeling and performance analysis of multimedia SoCs 多媒体soc的随机建模与性能分析

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) Pub Date : 2013-07-15 DOI: 10.1109/SAMOS.2013.6621117

Balaji Raman, Ayoub Nouri, Deepak Gangadharan, M. Bozga, A. Basu, Mayur Maheshwari, Axel Legay, S. Bensalem, S. Chakraborty

引用次数: 10

MGSim — A simulation environment for multi-core research and education MGSim -多核研究和教育的模拟环境

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) Pub Date : 2013-07-15 DOI: 10.1109/SAMOS.2013.6621109

R. Poss, M. Lankamp, Qiang Yang, Jian Fu, M. I. Uddin, C. Jesshope

引用次数: 19

Dynamic task mapping onto multi-core architectures through stream rewriting 通过流重写将动态任务映射到多核架构

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) Pub Date : 2013-07-15 DOI: 10.1109/SAMOS.2013.6621123

Lars Middendorf, C. Zebelein, C. Haubelt

引用次数: 9

FlexCore: Implementing an exposed datapath processor FlexCore:实现一个公开的数据路径处理器

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) Pub Date : 2013-07-15 DOI: 10.1109/SAMOS.2013.6621139

Magnus Själander, P. Larsson-Edefors

引用次数: 3

Rethinking computer architecture for throughput computing 重新思考吞吐量计算的计算机体系结构

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) Pub Date : 2013-07-15 DOI: 10.1109/SAMOS.2013.6621096

Wen-mei W. Hwu

引用次数: 1

TimeCube: A manycore embedded processor with interference-agnostic progress tracking TimeCube:一种多核嵌入式处理器，具有干扰不可知的进程跟踪

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) Pub Date : 2013-07-15 DOI: 10.1109/SAMOS.2013.6621127

Anshuman Gupta, J. Sampson, M. Taylor

{"title":"TimeCube: A manycore embedded processor with interference-agnostic progress tracking","authors":"Anshuman Gupta, J. Sampson, M. Taylor","doi":"10.1109/SAMOS.2013.6621127","DOIUrl":"https://doi.org/10.1109/SAMOS.2013.6621127","url":null,"abstract":"Recently introduced processors such as Tilera's Tile Gx100 and Intel's 48-core SCC have delivered on the promise of high performance per watt in manycore processors, making these architectures ostensibly as attractive for low-power embedded processors as for cloud services. However, these architectures space-multiplex the microarchitectural resources between many threads to increase utilization, which leads to potentially large and varying levels of interference. This decorrelates CPU-time from actual application progress and decreases the ability of traditional software to accurately track and finely control application progress, hindering the adoption of manycore processors in embedded computing. In this paper we propose Progress Time as the counterpart of CPU-time in space-multiplexed systems and show how it can be used to track application progress. We also introduce TimeCube, a manycore embedded processor that uses dynamic execution isolation and shadow performance modeling to provide an accurate online measurement of each application's Progress Time. Our evaluation shows that a 32-core TimeCube processor can track application progress with less than 1% error even in the presence of a 6× average worst-case slowdown. TimeCube also uses Progress Times to perform online architectural resource management that leads to a 36% improvement in throughput compared to existing microarchitectural resource allocation schemes. Overall, the results argue for adding the requisite microarchitectural structures to support Progress Time in manycore chips for embedded systems.","PeriodicalId":382307,"journal":{"name":"2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114061829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

OpenCL code generation for low energy wide SIMD architectures with explicit datapath 具有显式数据路径的低能耗宽SIMD架构的OpenCL代码生成

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) Pub Date : 2013-07-15 DOI: 10.1109/SAMOS.2013.6621141

Dongrui She, Yifan He, Luc Waeijen, H. Corporaal

引用次数: 11