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2014 Symposium on VLSI Circuits Digest of Technical Papers最新文献

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A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS 基于28nm数字CMOS的70db SNDR 200ms /s 2.3 mW动态流水线SAR ADC
2014 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 2014-06-10 DOI: 10.1109/VLSIC.2014.6858451
B. Verbruggen, K. Deguchi, Badr Malki, J. Craninckx
{"title":"A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS","authors":"B. Verbruggen, K. Deguchi, Badr Malki, J. Craninckx","doi":"10.1109/VLSIC.2014.6858451","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858451","url":null,"abstract":"We present a 200 MS/s 2x interleaved 14 bit pipelined SAR ADC in 28nm digital CMOS. The ADC uses a new residue amplifier for low noise at low power, and incorporates interleaved channel time-constant calibration. The ADC achieves a peak SNDR of 70.7 dB at 200 MS/s while consuming 2.3 mW from an 0.9 V supply.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"326 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115871562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 81
2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology 采用22nm三栅极CMOS技术的第二代嵌入式DRAM，自刷新功率降低4倍
2014 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 2014-06-10 DOI: 10.1109/VLSIC.2014.6858415
M. Meterelliyoz, F. Al-amoody, U. Arslan, F. Hamzaoglu, L. Hood, M. Lal, Jeffrey L. Miller, Anand Ramasundar, D. Soltman, I. Wan, Yih Wang, Kevin Zhang
{"title":"2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology","authors":"M. Meterelliyoz, F. Al-amoody, U. Arslan, F. Hamzaoglu, L. Hood, M. Lal, Jeffrey L. Miller, Anand Ramasundar, D. Soltman, I. Wan, Yih Wang, Kevin Zhang","doi":"10.1109/VLSIC.2014.6858415","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858415","url":null,"abstract":"2nd generation 1Gbit 2GHz Embedded DRAM (eDRAM) with 4X lower self refresh power compared to prior generation is developed in 22nm Tri-Gate CMOS technology. Retention time has been improved by 3X (300us@95°C) by process and design optimizations. Source synchronous clocking is integrated in the design to reduce clock power without penalizing bandwidth. Charge pump power is reduced by 4X by employing comparator based regulation. Temperature controlled refresh enables minimum refresh power at all temperature conditions.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129377964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs
2014 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 2014-06-10 DOI: 10.1109/VLSIC.2014.6858367
Reum Oh, Byunghyun Lee, Sang-Woong Shin, Wonil Bae, Hundai Choi, Indal Song, Yun-Sang Lee, J. Choi, Chi-Wook Kim, Seong-Jin Jang, Joo-Sun Choi
{"title":"Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs","authors":"Reum Oh, Byunghyun Lee, Sang-Woong Shin, Wonil Bae, Hundai Choi, Indal Song, Yun-Sang Lee, J. Choi, Chi-Wook Kim, Seong-Jin Jang, Joo-Sun Choi","doi":"10.1109/VLSIC.2014.6858367","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858367","url":null,"abstract":"For the demand of sever systems with high performance, high density and low power consumption, 3-D DDR4 SDRAM with TSVs was developed. In order to achieve higher data rate at lower voltage in comparison with precedent DDR3 SDRAM with TSVs, the placements of TSVs have been optimized without the penalty of chip size and the calibration method for reducing process mismatch between stacked DRAM chips is proposed. Additionally, new cell test method for stacked dies is adopted to keep costs down and the skewed self-refresh is proposed to reduce power noise. The IO speed of new DDR4 SDRAM with TSVs is increased to 2.4Gb/s at 1.2V.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130632583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM 一种128GB/s高带宽内存(HBM)堆叠DRAM的TSV连接精确测量与修复电路
2014 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 2014-06-10 DOI: 10.1109/VLSIC.2014.6858368
Dong-Uk Lee, Kyung Whan Kim, Kwan-Weon Kim, Kangseol Lee, S. Byeon, Jin-Hee Cho, H. Jin, S. K. Nam, Jaejin Lee, J. Chun, Sung-Joo Hong
{"title":"An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM","authors":"Dong-Uk Lee, Kyung Whan Kim, Kwan-Weon Kim, Kangseol Lee, S. Byeon, Jin-Hee Cho, H. Jin, S. K. Nam, Jaejin Lee, J. Chun, Sung-Joo Hong","doi":"10.1109/VLSIC.2014.6858368","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858368","url":null,"abstract":"For the heterogeneous-structured high bandwidth memory (HBM) DRAM, it is important to guarantee the reliability of TSV connections. An exact TSV current scan and repair method is proposed, that uses similar to the correlated double sampling method. The register-based pre-repair method improves testability. The measurement results for thousands of TSV shows impedance distribution under 0.1 ohm. Methods are integrated in 8Gb HBM stacked DRAM using 29nm process.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117016096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
R-processor: 0.4V resilient processor with a voltage-scalable and low-overhead in-situ error detection and correction technique in 65nm CMOS R-处理器：0.4V弹性处理器，采用65纳米CMOS，具有电压可升级和低开销原位错误检测和纠正技术
2014 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 2014-06-10 DOI: 10.1109/VLSIC.2014.6858421
Seongjong Kim, Mingoo Seok
{"title":"R-processor: 0.4V resilient processor with a voltage-scalable and low-overhead in-situ error detection and correction technique in 65nm CMOS","authors":"Seongjong Kim, Mingoo Seok","doi":"10.1109/VLSIC.2014.6858421","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858421","url":null,"abstract":"This paper presents a design approach for upgrading the resiliency of ultra-low-voltage (ULV) microprocessors through a voltage-scalable and low-overhead in-situ error detection and correction (EDAC) technique. Particular efforts are made to overcome the poor voltage scalability and area/energy/throughput overhead of the existing EDAC techniques when applied to ULV designs. The 0.4 V, 16 b microprocessor employing the proposed EDAC and dynamic frequency scaling schemes is demonstrated in 65 nm. The microprocessor can (1) automatically modulate fCLK based on error flags across static/slow variations and (2) in-situ detect and correct the errors from fast dynamic variations, virtually eliminating timing margins. At a typical process/voltage/temperature (PVT) corner, the proposed design achieves 4.9× throughput and 59% energy efficiency improvement at only 9.5% area overhead over the baseline design under the worst-case timing margin.","PeriodicalId":381216,"journal":{"name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125812785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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