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VHDL-Simulation und -Synthese最新文献

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7. Entwurf von Zustandsautomaten
VHDL-Simulation und -Synthese Pub Date : 2020-10-26 DOI: 10.1515/9783110673463-007
{"title":"7. Entwurf von Zustandsautomaten","authors":"","doi":"10.1515/9783110673463-007","DOIUrl":"https://doi.org/10.1515/9783110673463-007","url":null,"abstract":"","PeriodicalId":377878,"journal":{"name":"VHDL-Simulation und -Synthese","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132397639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
2. VHDL-Entwurf einfacher Schaltnetze 2. 那是一场灾难
VHDL-Simulation und -Synthese Pub Date : 2020-10-26 DOI: 10.1515/9783110673463-002
{"title":"2. VHDL-Entwurf einfacher Schaltnetze","authors":"","doi":"10.1515/9783110673463-002","DOIUrl":"https://doi.org/10.1515/9783110673463-002","url":null,"abstract":"","PeriodicalId":377878,"journal":{"name":"VHDL-Simulation und -Synthese","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134213640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
6. FPGA-Synthese und Implementierung synchroner Schaltungen 6. 标题合成和实现电路
VHDL-Simulation und -Synthese Pub Date : 2020-10-26 DOI: 10.1515/9783110673463-006
{"title":"6. FPGA-Synthese und Implementierung synchroner Schaltungen","authors":"","doi":"10.1515/9783110673463-006","DOIUrl":"https://doi.org/10.1515/9783110673463-006","url":null,"abstract":"","PeriodicalId":377878,"journal":{"name":"VHDL-Simulation und -Synthese","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130699648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
9. Entwurf eines RISC-Prozessors 9. 原始集成电路设计
VHDL-Simulation und -Synthese Pub Date : 2020-10-26 DOI: 10.1515/9783110673463-009
{"title":"9. Entwurf eines RISC-Prozessors","authors":"","doi":"10.1515/9783110673463-009","DOIUrl":"https://doi.org/10.1515/9783110673463-009","url":null,"abstract":"","PeriodicalId":377878,"journal":{"name":"VHDL-Simulation und -Synthese","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131799628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Inhaltsverzeichnis 目录。
VHDL-Simulation und -Synthese Pub Date : 2020-10-26 DOI: 10.1515/9783110673463-toc
{"title":"Inhaltsverzeichnis","authors":"","doi":"10.1515/9783110673463-toc","DOIUrl":"https://doi.org/10.1515/9783110673463-toc","url":null,"abstract":"","PeriodicalId":377878,"journal":{"name":"VHDL-Simulation und -Synthese","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130537881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
13. Anhang 13. 附件
VHDL-Simulation und -Synthese Pub Date : 1978-12-31 DOI: 10.1515/9783110586411-013
Regina Gente
{"title":"13. Anhang","authors":"Regina Gente","doi":"10.1515/9783110586411-013","DOIUrl":"https://doi.org/10.1515/9783110586411-013","url":null,"abstract":"","PeriodicalId":377878,"journal":{"name":"VHDL-Simulation und -Synthese","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121878497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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