{"title":"Look-up tables (LUTs) for multiple-valued, combinational logic","authors":"A. Sheikholeslami, R. Yoshimura, P. Gulak","doi":"10.1109/ISMVL.1998.679468","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679468","url":null,"abstract":"The use of Look-Up Tables (LUTs) is extended from binary to multiple-valued logic (MVL) circuits. A multiple-valued LUT can be implemented using both current-mode and voltage-mode techniques, reducing the transistor count to half compared to that of a binary implementation. Two main applications for multiple-valued LUTs are multiple-valued FPGAs and intelligent memories. An FPGA uses a LUT as a generic logic block to provide programmability. In an intelligent memory, a multiple-valued LUT is added in the Y-decoder section to facilitate simple mathematical operations on the stored digits. An FFT operation is used as an example in this paper to illustrate how a multiple-valued LUT can be beneficial.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125413960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evolutionary methods in the design of quaternary digital circuits","authors":"C. Moraga, Wenjun Wang","doi":"10.1109/ISMVL.1998.679309","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679309","url":null,"abstract":"This paper is concerned with the design of optimal CMOS 4-valued digital circuits. After an analysis of the problems in the logic design of quaternary circuits it is shown that evolutionary methods may be effectively used do obtain optimal cost-table based circuit realizations of both full specified and incompletely specified quaternary functions.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129559734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multiple-valued hyperstructures","authors":"I. Rosenberg","doi":"10.1109/ISMVL.1998.679509","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679509","url":null,"abstract":"An n-ary hyperoperation on A is a map from A/sup n/ into the set P of nonvoid subsets of A. A hyperclone on A is a set of hyperoperations on A containing all projections and closed with respect to a natural composition. Although special hyperalgebras, like hypergroups, hyperrings etc., have been studied for 6 decades there is no universal-algebra type theory for hyperalgebras. We try to close this gap by embedding hyperoperations on A into the set Q of all /spl sube/-isotone operations on P. The very crucial compatible relations are introduced through this embedding. For A finite we search for a general completeness criterion and the related maximal hyperclones via the maximal subclones of Q. For this we determine the position of Q in the lattice of clones on P and initiate the study of such meet-reducible clones. We find all such clones of the form Q/spl cap/Pol /spl rho/ where /spl rho/ is a proper unary relation on P, toe reduce the case of equivalence relations and show that two types of maximal clones on P produce no maximal subclone of Q.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123120725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An error reducing approach to machine learning using multi-valued functional decomposition","authors":"C. Files, M. Perkowski","doi":"10.1109/ISMVL.1998.679330","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679330","url":null,"abstract":"This paper considers minimization of incompletely specified multi-valued functions using functional decomposition. While functional decomposition was originally created for the minimization of logic circuits, this paper uses the decomposition process for both machine learning and logic synthesis of multi-valued functions. As it turns out, the minimization of logic circuits can be used in the concept of \"learning\" in machine learning, by reducing the complexity of a given data set. A main difference is that machine learning problems normally have a large number of output don't cares. Thus, the decomposition technique presented in this paper is focused on functions with a large number of don't cares. There have been several papers that have discussed the topic of using multi-valued functional decomposition for functions with a large number of don't cares. The novelty brought with this paper is that the proposed method is structured to reduce the resulting \"error\" of the functional decomposer where \"error\" is a measure of how well a machine learning algorithm approximates the actual, or true function.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115328689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Ternary decision diagrams with inverted edges and cofactoring-an application to discrete neural networks synthesis","authors":"L. Macchiarulo, P. Civera","doi":"10.1109/ISMVL.1998.679289","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679289","url":null,"abstract":"A central issue in multiple valued logic design is the definition of a complete methodology that starting from a raw input/output description of the desired behaviour could give a detailed netlist of a circuit implementing it. The use of Decision Diagram techniques to represent multiple-valued functions, together with new learning algorithms derived from Neural Network theory may help in building such a methodology. It is possible to integrate all steps in a complete CAD synthesis technique.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115828777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Development of InGaAs-based multiple-junction surface tunnel transistors for multiple-valued logic circuits","authors":"T. Baba, T. Uemura","doi":"10.1109/ISMVL.1998.679267","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679267","url":null,"abstract":"Multiple negative-differential-resistance (NDR) characteristics (up to six NDRs) are demonstrated by fabricating multiple-junction surface tunnel transistors (MJ-STTs) using an InGaAs material system. The tunneling current density is 500 times larger than that for a GaAs-based MJ-STT as well as higher peak-to-valley ratios (about 5). As an application of MJ-STTs for binary and multiple-valued logic, a programmable NAND/NOR logic circuit and a three-valued inverter circuit are implemented monolithically. Proper circuit operations of these circuits are confirmed using an oscillatory supply voltage.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115968201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On low cost realization of multiple-valued logic functions","authors":"Takahiro Hozumi, O. Kakusho, Y. Hata","doi":"10.1109/ISMVL.1998.679448","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679448","url":null,"abstract":"This paper evaluates the number of product terms needed in the minimal sum-of-products expressions for extended product and sum operators based on Shannon expansion. We show definitions of a product-type and a sum-type function. According to the definitions, we list all product-type and sum-type functions by investigating all three-valued two-variable functions. Using the functions, we examine the numbers of product terms needed in the minimal sum-of-product expressions for any three-valued two-variable functions and show that the MODSUM-of-MINs expressions require fewest product terms of the all. On investigating all four-valued sum-of-products expressions, it is shown that MODSUM-of-MINs expressions require the fewest product terms. Furthermore, on investigating the expressions with the weak conditions for the product-type function. We find some expressions requiring fewer product terms than the MODSUM-of-MINs expressions.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131461080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fast multi-polarity complex Hadamard transform for logic functions","authors":"B. Falkowski","doi":"10.1109/ISMVL.1998.679332","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679332","url":null,"abstract":"A new formulation of Fast Multi-Polarity Complex Hadamard Transform has been introduced. Forward and inverse transformation kernels and the ways of recursive generation of transform matrices by using Kronecker products of elementary matrices have been given. Mutual relations among transform matrices and spectra for arbitrary polarities have been presented. Efficient ways of calculating spectra for logic functions through decision diagrams are also shown. Half-spectrum property is used to reduce the computational requirements for both fast transforms and decision diagrams based calculations.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126518538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multiple-valued logics for theorem-proving in first order logic with equality","authors":"R. Bignall, M. Spinks","doi":"10.1109/ISMVL.1998.679313","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679313","url":null,"abstract":"We outline a method for proving theorems in first-order logic with equality using some equational logics and their associated multiple-valued propositional logics, and describe an application of the method that makes use of the automated theorem-prover Otter to prove a range of theorems from the TPTP library of problems in first-order logic with equality.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115209979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Minimization of exclusive sums of multi-valued complex terms for logic cell arrays","authors":"N. Song, M. Perkowski","doi":"10.1109/ISMVL.1998.679272","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679272","url":null,"abstract":"The paper proposes a new layout-driven multi-level logic factorization methodology for regular arrays of two-input cells, that can find practical applications in fine-grain FPGA design, standard cell, gate matrix layout and sub-micron technologies. A new factorization algorithm for AND/OR/EXOR logic with multi-valued literals is introduced, that has application to minimization of Logic Cell Arrays, and improves on previous results. It is shown that an extended cube representation and efficient minimization rules can be used, that generalize the ESOP minimization approach. Results of program MINICT demonstrate big area savings for several functions.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127733537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}