2011 IEEE 61st Electronic Components and Technology Conference (ECTC)最新文献

{"title":"Inline thermal transient testing of high power LED modules for solder joint quality control","authors":"G. Elger, R. Lauterbach, Kurt Dankwart, C. Zilkens","doi":"10.1109/ECTC.2011.5898733","DOIUrl":"https://doi.org/10.1109/ECTC.2011.5898733","url":null,"abstract":"Heat management and reliability is essential for high power LED packages, e.g. for high temperature application like automotive lightning or application with very long lifetimes like street lightning. To reduce the LED junction temperature a low thermal resistance is realized by mounting the LED packages on heat spreaders or boards with good heat conduction. The joint between package and heat spreader, very often a solder joint due to the good thermal conductivity of the solder material, need to be void and gap free to achieve a good heat conduction and high reliability. The quality of solder joints of LED packages is usually controlled in production by X-ray and acoustic microscopy (CSAM). From a good solder joint, i.e. detection of no bad soldered area, a good thermal performance is concluded. The Thermal Transient Testing provides a method to measure the thermal resistance by measuring the forward voltage Vf(t) time dependent after a thermal power step, i.e. switching the drive current from high drive to low drive current. However, the k-factor, the linear dependence between Vf(t) of the LED and the real thermal power step needs to be measured to obtain the correct thermal resistance. We have developed an algorithm to enable inline thermal transient testing of LED modules without the need to measure the k-factor and the thermal power step. Instead of calculating the structural response function from the transient forward voltage, we evaluate the forward voltage in the time domain. For the development of the method we have set up a finite element (FE) model for our LED packages and performed transient thermal simulation. The FE model was fitted to the experimental data. We simulate the influence of void sizes and positions, gaps and joint thickness on the transient temperature curves. By comparing the measured sample with a known good sample we can evaluate the quality of the solder joint and calculate the thermal resistance. We apply the measurement method for quality control of the solder joints of our high power LED packages. The measurement method targets to replace X-ray or CSAM inspection within production. We compared CSAM inspection with the thermal resistance measurements. Thermal resistance and non soldered area are correlated for larger bad soldered areas. We achieved a detection limit of roughly 30% of bad soldered area.","PeriodicalId":377723,"journal":{"name":"2011 IEEE 61st Electronic Components and Technology Conference (ECTC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114969299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cost-effective lithography for TSV-structures","authors":"U. Vogler, F. Windrich, A. Schenke, R. Volkel, Matthias Bottcher, Ralph Zoberbier","doi":"10.1109/ECTC.2011.5898696","DOIUrl":"https://doi.org/10.1109/ECTC.2011.5898696","url":null,"abstract":"3D and Through-Silicon Vias (TSV) simplify and speed-up the chip-to-chip communication. The usage will enable manufacturers to increase the device performance, while cost effectively reducing overall size. The key issue for this new technology is a cost-effective drilling of holes into the substrate and the possibility to realize high density multilayer redistribution and bump layers (RDL). The most promising approach is to use photolithography with various thin and thick resist applications to etch the vias by deep reactive ion etching (DRIE) and to build up the RDL applicable on substrates with high topography. The structures to produce TSVs do not seem to be a challenge in nowadays production. The diameters are typically 1 to 50μm resp. 20 to 200μm for bumps, while the front-end industry manufactures in 32 node today. But to establish 3D IC and TSV, the production preferably should be capable to provide cost-effective lithography on thinned wafers at competitive price levels. This paper will present a method to expand the current production limits of Mask Aligners. Using special features on the mask in combination with a novel illumination optics, it is possible to increase the throughput, the expose gap and/or decrease the minimum structure size. This kind of technologie will enhance the range of ∗D wafer level packing lithography applications on high topography substrates. The so called “MO Exposure Optics” from SUSS stabilizes the illumination of mask-aligners and allows to freely shape the angular spectrum of the radiation on the mask. So it is possible to transfer well know principles in projection lithography to mask-aligner lithography like Optical Proximity Correction (OPC) or Source Mask Optimization (SMO). It enables also the usage of binary optical elements to enhance the production of high density TSV and RDL / bump structures.","PeriodicalId":377723,"journal":{"name":"2011 IEEE 61st Electronic Components and Technology Conference (ECTC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115004757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Synthesis of high quality, closely packed vertically aligned carbon nanotube array and a quantitative study of the influence of packing density on the collective thermal conductivity","authors":"W. Gu, Wei Lin, Yagang Yao, C. Wong","doi":"10.1109/ECTC.2011.5898669","DOIUrl":"https://doi.org/10.1109/ECTC.2011.5898669","url":null,"abstract":"In this work, we present the effect of packing density of vertically aligned carbon nanotube (VACNT) array on its thermal conductivity, as a step closer to its application in thermal interface materials (TIMs). High quality, closely packed VACNT array is synthesized by chemical vapor deposition (CVD) method. Cyclic catalyst deposition is performed to increase the packing density of VACNT array. Liquid precursor is applied to adjust the growth rate and keep the uniformity of the final thickness of the samples. The thermal conductivity of the VACNT array is greatly enhanced with the packing density, from 45.2 W/m K to 75.5 W/m K.","PeriodicalId":377723,"journal":{"name":"2011 IEEE 61st Electronic Components and Technology Conference (ECTC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115431784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced solder TSV filling technology developed with vacuum and wave soldering","authors":"Young-Ki Ko, H. Fujii, Y. Sato, Chang-Woo Lee, S. Yoo","doi":"10.1109/ECTC.2011.5898806","DOIUrl":"https://doi.org/10.1109/ECTC.2011.5898806","url":null,"abstract":"This research investigated advanced filling technology, different from existing technologies, for the purpose of 3D layering on electronic circuits. Filling with molten solder causes a pressure difference between the upper and lower part of the wafer, to overcome surface tension of the through via holes, and then due to pressure difference molten solder is filled into the TSV. The wafer thickness was 100–200μm with holes of diameter 20∼30μm. The TSVs were formed by deep reactive ion etching (DRIE). A wetting layer of Ti/Cu or Au was sputtered on the wall of the TSVs. Due to pressure differences between upper and lower parts, the molten solder filled into the Through Silicon Via (TSV). Vacuum Pressure was between 0.02MPa and 0.08MPa. The filling speed was under 3 seconds, much higher than conventional methods. Cross-sectional micrographs were taken with a field emission second electron microscope (FE-SEM).","PeriodicalId":377723,"journal":{"name":"2011 IEEE 61st Electronic Components and Technology Conference (ECTC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121246146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Next generation fine pitch Cu Pillar technology — Enabling next generation silicon nodes","authors":"M. Gerber, C. Beddingfield, Shawn M. O'connor, Min Yoo, Minjae Lee, Daebyoung Kang, SungSu Park, C. Zwenger, R. Darveaux, R. Lanzone, KyungRok Park","doi":"10.1109/ECTC.2011.5898576","DOIUrl":"https://doi.org/10.1109/ECTC.2011.5898576","url":null,"abstract":"There has been a growing need for fine pitch flip chip technology in support of next generation communication devices with increasing die complexities. The increase in functionality which drives a larger number of signal I/O's in combination with small die size requirements as a result of transistor size reductions have driven the need to investigate finer die interconnect pitches. Traditional solder or Cu Pillar interconnect pitches of 150um to 200um that are currently used in both low and high end flip chip applications are now facing a number of technical limitations as device scaling requirements push the limits of flip chip pad density per square mm of silicon. This paper will review the process development and advancement of several next generation fine pitch Cu Pillar bumping and assembly processes, with pitches less than 60um, that are focused on addressing the challenges seen on silicon nodes such as 65nm and beyond.","PeriodicalId":377723,"journal":{"name":"2011 IEEE 61st Electronic Components and Technology Conference (ECTC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127096424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Interfacial reliability and micropartial stress analysis between TSV and CPB through NIT and MSA","authors":"Gyujei Lee, Yu-hwan Kim, Suk-woo Jeon, Kwang-yoo Byun, D. Kwon","doi":"10.1109/ECTC.2011.5898700","DOIUrl":"https://doi.org/10.1109/ECTC.2011.5898700","url":null,"abstract":"As Moore predicted in 1965, the scale of microelectronic devices continues to diminish at tremendous speed, and today the limitations of conventional 2D scaling make such 3D applications as TSV (through-silicon via) and high-stacked thin-die packaging technologies extremely attractive. However, their complicated structures and thermal-cycled processes generate enormous interfacial stresses. In particular, TSV-to-CPB (copper pillar bump)-stacked structures manufactured under various processing conditions have serious stress-induced reliability problems: stresses can be high enough to cause delaminated or open-crack failures. Many technologies have been developed for measuring residual stress, but destructive techniques such as the hole-drilling and cutting methods are too bulky to use at microscales and non-destructive techniques such as XRD (X-ray diffraction), BN (Barkhausen noise) and the curvature method using the Stoney equation yield averaged results that are inappropriate in the local assessment of TSV and CPB interfaces. NIT (nanoinstrumented indentation testing), on the other hand, offers many advantages since it can give a micropartial characterization of stress using the load difference between samples with different residual stresses at the same depth. Here we introduce an algorithm to measure the micropartial residual stress between CPB and TSV through nanoinstrumented indentation testing. To verify our measured outputs, we observe cross-sectioned microstructure of TSV and CPB using an ion miller and ion-beam image by FIB (focused ion beam), and discuss the textures of variously structured and processed TSV and CPB interfaces. In addition, we used finite element analysis (ABSYS) to simulate the stress distribution around them. Our study will, we hope, be useful in reliability-based quantitative design by defining keep-out zones between TSVs.","PeriodicalId":377723,"journal":{"name":"2011 IEEE 61st Electronic Components and Technology Conference (ECTC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127176689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electromagnetic-SPICE modeling and analysis of 3D power network","authors":"Zheng Xu, Jian-Qiang Lu, B. Webb, J. Knickerbocker","doi":"10.1109/ECTC.2011.5898820","DOIUrl":"https://doi.org/10.1109/ECTC.2011.5898820","url":null,"abstract":"Accurate modeling and estimation of 3D power network electrical performance are vitally important to aid the 3D integration and packaging design. In order to achieve high accuracy, we combine the electromagnetic (EM) and analytic simulations in this work to evaluate the electrical performance of a 3D power network, which consists of Cu through-strata-vias (TSVs), solders, micro-solders, and on-chip power grids. We intentionally partition the real stack-up structure of 3D power network into separated components, electromagnetically extract all the passive elements (resistance, inductance, con­ductance, and capacitance, i.e., RLGC) for each component at certain frequency points of interest. We then assemble all the components again into a corresponding SPICE model of 3D power network and import EM-extracted RLGC values to analyze the overall 3D system power performance. The number of stacked ICs, floorplanning of TSV/micro-solders, operating frequency of 3D system, and characteristics of decoupling capacitance are examined to unveil several 3D power delivery design implications.","PeriodicalId":377723,"journal":{"name":"2011 IEEE 61st Electronic Components and Technology Conference (ECTC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126052165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Through Silicon Via interposer for millimetre wave applications","authors":"T. Lim, Y. Khoo, C. Selvanayagam, D. Ho, Rui Li, Xiaowu Zhang, Gao Shan, Xiong Yong Zhong","doi":"10.1109/ECTC.2011.5898570","DOIUrl":"https://doi.org/10.1109/ECTC.2011.5898570","url":null,"abstract":"A novel Through Silicon Via (TSV) structure to mitigate the high electrical loss at high frequency is presented here. At low frequency, the loss for the TSV is caused mainly by the material loss of the Silicon (Si) substrate due to its low resistivity. However, at millimetre wave (mmWave) frequency range, especially above 50GHz, in addition to the insertion loss, the return loss due to impedance mismatched becomes significant. These losses become a serious setback for the Si Interposer for the mmWave applications. To overcome these losses, polymer cavity formed in the Si substrate with TSV is developed. The polymer has lower loss tangent and lower dielectric constant than Si. These properties can help to reduce the insertion loss and the return loss. Depending on the requirement, multiple set of TSV can be formed on the polymer cavity to provide higher interconnect density. From the simulation results, the new polymer cavity TSV at 100GHz have an insertion loss and return loss of ∼0.2dB and less than −25dB, respectively. On the other hand, conventional high resistivity TSV has an insertion loss and return loss of ∼1.4dB and more than −10dB, respectively, at the same frequency. For higher frequency range, the performance of the polymer cavity TSV is approximately consistent, but the conventional TSV deteriorated drastically. In this paper, the design, fabrication process and the measurement results are presented. The prototype polymer cavity TSV via-line-via test vehicle has a measured insertion loss of less than 1dB and a return loss of better than −10dB through the frequency range up to 110Gz.","PeriodicalId":377723,"journal":{"name":"2011 IEEE 61st Electronic Components and Technology Conference (ECTC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122743563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Embedded discrete passives technology for bandage-type medical sensors of E-healthcare system","authors":"B. Lee, S. Booh, K. Shin","doi":"10.1109/ECTC.2011.5898683","DOIUrl":"https://doi.org/10.1109/ECTC.2011.5898683","url":null,"abstract":"E-healthcare utilizes the latest information and communication technology (ICT) in healthcare. It is viable by three major elements of a medical sensor, a gateway and a server. The medical sensor worn on users' or patients' body acquires such bio-signals as ECG (Electro Cardio Graphic), body temperature and blood oxygen saturation, and wireless transmits the signals to the gateway such as a cell phone. The bio-signal information is finally sent to the server at hospitals through cellular network and then reversely real-time diagnosis and treatment to the users or patients is made from doctors or nurses. Since users have to wear the medical sensor on their body during their everyday life, the sensors are required to be thin, small and flexible considering the users comfortableness. This study will explore embedded discrete passive technology, which enables thin and flexible bandagelike E-healthcare sensors.","PeriodicalId":377723,"journal":{"name":"2011 IEEE 61st Electronic Components and Technology Conference (ECTC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122887827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Prospects and limits in wafer-level-packaging of image sensors","authors":"M. Wilke, F. Wippermann, K. Zoschke, M. Toepper, O. Ehrmann, H. Reichl, K. Lang","doi":"10.1109/ECTC.2011.5898775","DOIUrl":"https://doi.org/10.1109/ECTC.2011.5898775","url":null,"abstract":"The ongoing efforts of increasing the resolution of image sensors for consumer products and the simultaneous demand for small camera systems led to a miniaturization in pixel sizes down to 1.4μm. This technological progress enables the fabrication of high pixel count imagers with comparably small dimensions (e.g. 9MPix with 4.88mm × 3.66mm / 3MPix with 2.86mm × 2.15mm). Further on, besides the impact of the pixel size on the lateral dimensions of the imager, manufacturing and packaging issues of the optical components and their integration with the imager influence the miniaturization. There are two effects which determine the lower limit of reasonable pixel miniaturization. Firstly, the increasing single-to-noise characteristics of the pixel leading to noisy images especially perturbing under low light conditions. Secondly, the diffraction limits which determines the smallest possible spot size when using a “perfect” lens without any spot blurring aberrations. As the latter depends from the f-number of the system, pixel miniaturization demands high speed lenses (low f-numbers) which additionally complicates the optical design and challenges their fabrication. The enabling key technology for wafer level packaging of camera systems based on top-side illuminated imagers are Through Silicon Vias (TSV) because they allow a redistribution on the backside of the wafer wherefore the active side remains unaffected and can be completely used for the optic assembly. Due to comparably relaxed pitches of the contact pads of mostly more than 100μm in most imaging applications, tapered vias with a polymer passivation are the straight forward approach and an economic reasonable TSV technology. Spray coating of polymers allows the use of low cure temperature materials also with severe topographies while spin coating can be a low cost alternative for applications where low silicon thicknesses of 40μm and below are allowed. Wafer bonding is the bridging technology which finally has to integrate the optics and the sensor part. Wafer stacks of up to a few millimeters have to be handled which can exhibit topographies on their backside while maintaining an accurate alignment of better than 5μm. The fabrication of camera packages using only wafer level technologies gets more complex and expensive the bigger the vertical dimension and/or the aspect ratio or shape of its comprising features becomes. The demands for a system integration on wafer level scales therefore with increasing pixel number and I/O — density. This paper outlines the prospects and limits of state of the art wafer-level-packaging technology for image sensor packaging with respect to the optical design. A process chain is presented for a micro camera device which was completely fabricated on wafer level having a die size of about 1mm × 1mm.","PeriodicalId":377723,"journal":{"name":"2011 IEEE 61st Electronic Components and Technology Conference (ECTC)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122956391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}