WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS最新文献

{"title":"PCB Image Defects Detection by Artificial Neural Networks and Resistance Analysis","authors":"Roman Melnyk, Vitalii Vorobii","doi":"10.37394/23201.2024.23.7","DOIUrl":"https://doi.org/10.37394/23201.2024.23.7","url":null,"abstract":"The approach contains the sequence of algorithms and formulas for image processing. They are single-layer neural networks, thinning, clustering, mathematical image comparison, and measurements of the trace length and width. All these procedures solve the task of selection and separation of the main objects in the printed circuit board: contacts, traces, and defects. The calculated features connect the conductance resistance of traces with the characteristics of defects. Imposing a tolerance on the distributed or concentrated changes of resistance it is possible to mark the defective and suspicious printed circuit boards.","PeriodicalId":376260,"journal":{"name":"WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS","volume":"36 7","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141107617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis and Mitigation of Harmonics for a Wastewater Treatment Plant Electrical System","authors":"Axel Rivas Bonilla, Ha Thu Le","doi":"10.37394/23201.2024.23.1","DOIUrl":"https://doi.org/10.37394/23201.2024.23.1","url":null,"abstract":"Power quality has become a pressing issue that demands solutions as power electronic equipment has been increasingly used in industrial sectors. One critical problem is how to mitigate harmful harmonics generated by the power electronic equipment. This study investigates harmonic distortion issues in a wastewater treatment plant to verify compliance with IEEE standard 519 using simulation software ETAP and realistic data from the plant. Harmonic quantification shows that the plant harmonic situation violates IEEE Standard 519 where harmonic levels exceed its voltage and current limits. Different methods were used to mitigate the harmonic situation where the core is using passive harmonic filters. It is found that the biggest contributor to the harmonic distortion is the system variable frequency drives. Using high-pulse variable frequency drives, such as 18-pulse, is proven to be beneficial for harmonic reduction. Further, installing passive harmonic filters in appropriate locations helps lower voltage and current harmonics to meet IEEE Std. 519 limits. However, adding a passive harmonic filter higher up the power distribution or adding passive filters to the feeder buses is not effective in lowering the Total Harmonic Distortion (THD) of the system. This would have the drawback of increasing the rating of the system bus voltages. Other findings include a lack of medium voltage passive filters on the market and high costs. The study contributes some insight understanding, experience, and methods for engineers when developing solutions for controlling harmonics in similar plants or industrial applications.","PeriodicalId":376260,"journal":{"name":"WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS","volume":"29 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139847556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis and Mitigation of Harmonics for a Wastewater Treatment Plant Electrical System","authors":"Axel Rivas Bonilla, Ha Thu Le","doi":"10.37394/23201.2024.23.1","DOIUrl":"https://doi.org/10.37394/23201.2024.23.1","url":null,"abstract":"Power quality has become a pressing issue that demands solutions as power electronic equipment has been increasingly used in industrial sectors. One critical problem is how to mitigate harmful harmonics generated by the power electronic equipment. This study investigates harmonic distortion issues in a wastewater treatment plant to verify compliance with IEEE standard 519 using simulation software ETAP and realistic data from the plant. Harmonic quantification shows that the plant harmonic situation violates IEEE Standard 519 where harmonic levels exceed its voltage and current limits. Different methods were used to mitigate the harmonic situation where the core is using passive harmonic filters. It is found that the biggest contributor to the harmonic distortion is the system variable frequency drives. Using high-pulse variable frequency drives, such as 18-pulse, is proven to be beneficial for harmonic reduction. Further, installing passive harmonic filters in appropriate locations helps lower voltage and current harmonics to meet IEEE Std. 519 limits. However, adding a passive harmonic filter higher up the power distribution or adding passive filters to the feeder buses is not effective in lowering the Total Harmonic Distortion (THD) of the system. This would have the drawback of increasing the rating of the system bus voltages. Other findings include a lack of medium voltage passive filters on the market and high costs. The study contributes some insight understanding, experience, and methods for engineers when developing solutions for controlling harmonics in similar plants or industrial applications.","PeriodicalId":376260,"journal":{"name":"WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS","volume":" 8","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139787816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis and Design of an Active Rectifier for Wireless Power Transfer in 90 nm CMOS Technology","authors":"Said EL Mouzouade, Karim El khadiri, A. Tahiri","doi":"10.37394/23201.2023.22.20","DOIUrl":"https://doi.org/10.37394/23201.2023.22.20","url":null,"abstract":"In this paper, an analysis and design of a new active rectifier used for wireless power transfer applications using 90 nm CMOS technology are presented. The proposed architecture of the active rectifier has mainly been chosen to improve the VCE and the PCE and also to eliminate the need for large on-chip capacitors. The proposed circuits eliminate the drop needed for conduction by replacing diode-connected nMOS devices with others controlled by an active circuit. The new architecture of the active rectifier has been designed, simulated, and laid out by Cadence Virtuoso using TSMC 90nm technology. The input range is 0–5 V, and the output voltage is 2.14 V, with the VCE and the PCE values of 82.9% and 86.2%, respectively. The layout utilizes a compact space of 0.0597 mm2 within the TSMC CMOS 90 nm technology.","PeriodicalId":376260,"journal":{"name":"WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS","volume":"62 5","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139445150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Construction of a Density-Controlled Traffic Light System","authors":"A. S. A, Okeke J. C, Ayanbisi O. W, A. T. E., Ogunwale E. I, Oladapo O. F, Araka I. O.","doi":"10.37394/23201.2023.22.18","DOIUrl":"https://doi.org/10.37394/23201.2023.22.18","url":null,"abstract":"This work introduces the application of piezoelectric sensors on the road which intersects to form a T juncture, the application of the sensor aids in regulating the control of traffic density on each side of the road. Traffic congestion as of today is caused by the improper management of time and eventually leads to traffic delays. This was undoubtedly observed during early hours when a lot of civilians head out to their workstations and during closing hours in the evenings. The increasing population and economic activities in urban areas contribute to higher vehicle ownership and usage, leading to more traffic on the roads. It is achieved from the general desire of people to achieve goals, which ultimately leads to daily overcrowding of the present transportation infrastructure. But despite attempts at solutions, everyone despises traffic congestion, and it only gets unfavorable. The objective of this project is to create a dynamic road signal that is based on density. The synchronization signals automatically change to detect intersection traffic density. The components required to build this project include the microcontroller (Arduino uno), LEDs (light emitting diodes), piezoelectric sensors, jumper wires, a 9 V battery, a switch, and an operational amplifier. The result of the work focuses on the detection of density from a sensor which will be constructed underground to operate as a counter for every vehicle that passes by as it will be powered by a battery of approximately 9 V. The sensor which is known as the piezoelectric sensor abides by the rule of piezoelectric effect, which states that the stress produced from a non-static object, or the mechanical energy produced from a moving object will produce an electric charge in response to the mechanical energy generated. The electric charge produced from the piezoelectric sensor will be transmitted to the microcontroller (Arduino Uno). Through the input stage of the signal received, the program in the microcontroller will command the light-emitting diode (LEDs) to function accordingly to the state of density detected from each side of the road. Thereby regulating the flow of traffic movement efficiently and accurately. Overall, the application of the piezoelectric sensor on the road can accurately detect the presence of a vehicle passing.","PeriodicalId":376260,"journal":{"name":"WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS","volume":"21 8","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139443289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of Low Power SAR ADC with Novel Regenerative Comparator","authors":"Amrita Sajja, S. Rooban","doi":"10.37394/23201.2023.22.19","DOIUrl":"https://doi.org/10.37394/23201.2023.22.19","url":null,"abstract":"This paper introduces two low-power design techniques for a successive approximation register (SAR) analog-to-digital converter (ADC) used in transmitting physiological signals. The first technique is called dual split switching, involving the use of a one-sided charge-scaling digital-to-analog converter (DAC) to minimize switching energy by reducing leakage in a dual transmission gate. The second technique, known as the set and reset phase, determines the amplification and comparison phases of the comparator. This approach reduces the delay time of the comparator through the use of a folded cascode pre-amplifier and a regenerative latch. The design includes a Serial-in-Parallel-Out (SIPO) N-bit register and SAR, implemented using negative edge-triggered D flip-flops (DFFs). To optimize power consumption, the supply voltage of the SAR ADC is set to 500 mV. The concept of a variable threshold is utilized throughout the design to enable operation with this lower supply voltage. The SAR ADC is designed to support a sampling rate of up to 1 Msps (mega-samples per second). The circuit is implemented using standard UMC180nm technology. According to the test results, the power consumption of the SAR ADC is only 29.06 uW, and the achieved sampling rate is 5 Ksps (kilo-samples per second). The maximum differential non-linearity (DNL) is measured to be +0.9/−0.82 least significant bits (LSBs).","PeriodicalId":376260,"journal":{"name":"WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS","volume":"48 19","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139442447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bounding Formulae for the Capacitance of a Cylindrical Two-dimensional Capacitor with Cartesian Orthotropic Dielectric Material","authors":"A. Baksa, I. Ecsedi","doi":"10.37394/23201.2023.22.15","DOIUrl":"https://doi.org/10.37394/23201.2023.22.15","url":null,"abstract":"This paper addresses the evaluation of a two-dimensional cylindrical capacitor featuring homogeneous Cartesian anisotropic dielectric material. The development of a bounding formula forms the crux of the investigation and is grounded in the principles of the Cauchy-Schwarz inequality, a mathematical concept widely acknowledged for establishing relationships between different mathematical entities. In the course of this study, a dual-sided bound is systematically derived for the circular cylindrical two-dimensional capacitor through the application of well-established inequality relations. These bounds play a pivotal role in setting limits on the capacitance of the system, providing valuable insights into its electrical behavior.","PeriodicalId":376260,"journal":{"name":"WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS","volume":"60 4","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138951694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fault Identification in Modified Hybrid Digital Pulse Width Modulation using Triple Modular Redundancy","authors":"P. Jegadeeshwari, N. Kirubakaran, S. Bharath, G. Nalinashini, G. Mahalakshmi, Deborah Sabhan","doi":"10.37394/23201.2023.22.16","DOIUrl":"https://doi.org/10.37394/23201.2023.22.16","url":null,"abstract":"In this paper, the fault analysis is performed for the identification in the Modified Hybrid Digital Pulse Width Modulation by making use of the Triple Modular Redundancy method. The developed algorithm is real time implemented using the Xilinx Artix 7 FPGA device. The Modified Hybrid Digital Pulse Width Modulation is designed for the purpose of minimizing the Turn-ON and Turn-OFF delays in the triggering event of the generated Digital Pulse Width Modulation. Though additional compensatory circuits are added for the delay reduction, the area utilization is still low when implemented in FPGA device. Also, the Triple Modular Redundancy consists of three times of MHDPWM signal generation to check for the fault occurrence. For the sake of validating the fault identification, the majority voter circuit is used that could find the error at the earliest. The proposed method is checked for errors by inducing within the VHDL code and trailed with multiple duty cycle values. The proposed fault identification method is validated for VLSI parameters such as area, delay and power.","PeriodicalId":376260,"journal":{"name":"WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS","volume":"17 5","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138952827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-level Electro-Thermal Simulation of Power PCB Electronic Modules for Motor Driving","authors":"K. Petrosyants, Igor A. Kharitonov, Mikhail S. Tegin","doi":"10.37394/23201.2023.22.14","DOIUrl":"https://doi.org/10.37394/23201.2023.22.14","url":null,"abstract":"A scheme of automated multi-level electro-thermal modeling of power PCB modules using software tools Comsol at the device construction level, SPICE tool at the circuit level, and Asonika-TM tool at board level was proposed to improve the conventional design approach. The effectiveness of the proposed methodology is demonstrated in the example of electro-thermal analysis of real power MOSFET driver circuit realized on PCB.","PeriodicalId":376260,"journal":{"name":"WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS","volume":"43 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139007768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA Implementation of High-Performance Truncated Rounding based Approximate Multiplier with High-Level Synchronous XOR-MUX Full Adder","authors":"G. Erna, G. Srihari, M. P. Kishore, Ashok Nayak B., M. Bharathi","doi":"10.37394/23201.2023.22.13","DOIUrl":"https://doi.org/10.37394/23201.2023.22.13","url":null,"abstract":"In research and development, the most emerging field in digital signal processing and image processing is rounded-based approximated signed and unsigned multipliers. In the present research, we propose some cutting-edge, Preformation, and logic simplification technology connected to processing the Discrete cosine transform (DCT) and Discrete wavelet transform (DWT) images for sharpening. This technology will yield a truncated shifter incorporated with logical XOR-MUX Full adder techniques. A reliable and cost-effective approximate signed and unsigned multiplier was created for the rounding method. While this more advanced technology includes many approximate multipliers, it sacrifices the ability to find the closest integer of a rounded value when combining signed and unsigned capabilities, resulting in higher absolute errors than other approximate multipliers based on rounding. This proposed work will introduce a novel method of Truncated Shifter Rounding-based Approximate Multiplier integrated with a High-Level Synchronous XOR-MUX Full Adder design to minimize the number of logic gates and power consumption in the multiplier architecture. The Truncated RoBA (Rounding-based Approximate Multiplier) with XOR MUX Full Adder will reduce the logic size in the shifter and the arithmetic circuit. The work will modify this rounding-based approximate multiplier to minimize area, delay, and power consumption. This proposed architecture will be integrated with two fundamental changes: firstly, its Barrel shifter method will be replaced with a truncated shifter multiplier with XOR MUX Full Adder, and secondly, the parallel prefix Brent Kung adder will be replaced with a carrying-save adder with XOR MUX Full Adder. Finally, this architecture was designed using Verilog-HDL and synthesized using the Xilinx Vertex-5 FPGA family, targeting the device Xc7Vx485tFFg1157-1. It resulted in a reduction of area LUT (34%), power (1%), delay (32%), and error analysis (75%) when compared to the existing RoBA.","PeriodicalId":376260,"journal":{"name":"WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS","volume":"8 2","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138603051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}