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Software synthesis from the dataflow interchange format 软件从数据流合成交换格式
Software and Compilers for Embedded Systems Pub Date : 2005-09-29 DOI: 10.1145/1140389.1140394
Chia-Jui Hsu, S. Bhattacharyya
{"title":"Software synthesis from the dataflow interchange format","authors":"Chia-Jui Hsu, S. Bhattacharyya","doi":"10.1145/1140389.1140394","DOIUrl":"https://doi.org/10.1145/1140389.1140394","url":null,"abstract":"Specification, validation, and synthesis are important aspects of embedded systems design. The use of dataflow-based design environments for these purposes is becoming increasingly popular in the domain of digital signal processing (DSP). The dataflow inter-change format (DIF) [11] and the associated DIF package have been developed for specifying, working with, and transferring dataflow-based DSP designs across tools. In this paper, we present the newly developed DIF-to-C software synthesis framework for automatically generating monolithic C-code implementations from DSP system specifications that are programmed in DIF. This framework allows designers to efficiently explore the complex range of implementation tradeoffs that are available through various dataflow-based techniques for scheduling and memory management. Furthermore, the DIF-to-C framework provides a standard, vendor-neutral mechanism for linking coarse grain data-flow optimizations with fine grain hand-optimized libraries and the large body of optimization techniques in the area of C compilers for DSP. Through experiments involving several DSP applications, we demonstrate the novel and useful capabilities of our DIF-to-C software synthesis framework.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133613329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 105
The bit-reversal SDRAM address mapping 位反转的SDRAM地址映射
Software and Compilers for Embedded Systems Pub Date : 2005-09-29 DOI: 10.1145/1140389.1140396
Jun Shao, B. Davis
{"title":"The bit-reversal SDRAM address mapping","authors":"Jun Shao, B. Davis","doi":"10.1145/1140389.1140396","DOIUrl":"https://doi.org/10.1145/1140389.1140396","url":null,"abstract":"The performance contributions of SDRAM address mapping techniques in the main memory of an embedded system are studied and examined. While spatial locality existing in the access stream increases SDRAM row hit rate, it also increases row conflicts. Mapping of the physical address bits into SDRAM column, row, bank and rank index impacts system performance significantly. A novel address mapping scheme, called bit-reversal, is described and experimentally compared against known methods. The bit-reversal address mapping increases SDRAM row hit rate from 43% to 66% by distributing conflicting memory accesses over independent SDRAM banks. Bit-reversal address mapping reduces the average memory access latency by 26%-29% over other methods, resulting in a 11.7%-13.5% reduction of total execution time. The configuration space of bit-reversal address mapping is explored. Finally, limited studies examining the impact of address mapping techniques in conjunction with SDRAM controller policy and virtual paging illustrate that mapping is better suited to virtual memory free embedded systems than desktop workstations incorporating paging mechanisms.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123887685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Generic software pipelining at the assembly level 程序集级别的通用软件流水线
Software and Compilers for Embedded Systems Pub Date : 2005-09-29 DOI: 10.1145/1140389.1140395
Daniel Kästner, Markus Pister
{"title":"Generic software pipelining at the assembly level","authors":"Daniel Kästner, Markus Pister","doi":"10.1145/1140389.1140395","DOIUrl":"https://doi.org/10.1145/1140389.1140395","url":null,"abstract":"Software used in embedded systems is subject to strict timing and space constraints. The growing software complexity creates an urgent need for fast program execution under the constraint of very limited code size. However, even modern compilers produce code whose quality often is far away from the optimum. The PROPAN system is a postpass optimization framework that enables high-quality machine-dependent postpass optimizers to be generated from a concise hardware specification. The postpass approach allows to enhance the code quality of existing compilers and offers a smooth integration into existing development tool chains. In this article we present an adaptation of the modulo scheduling software pipelining algorithm to the postpass level. The implementation is fully retargetable and has been incorporated in the PROPAN system. The differences of postpass modulo scheduling compared to the standard version of the algorithm are outlined. Experimental results conducted on the Philips TriMedia TM1000 processor demonstrate that modulo scheduling can be applied at the postpass level and allows to achieve a significant code speedup with moderate code size increase.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129394146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
MTP: a Petri net-based framework for the analysis and transformation of SystemC designs MTP:用于分析和转换SystemC设计的基于Petri网的框架
Software and Compilers for Embedded Systems Pub Date : 2005-09-29 DOI: 10.1145/1140389.1140400
N. Savoiu
{"title":"MTP: a Petri net-based framework for the analysis and transformation of SystemC designs","authors":"N. Savoiu","doi":"10.1145/1140389.1140400","DOIUrl":"https://doi.org/10.1145/1140389.1140400","url":null,"abstract":"Shrinking time-to-market requires faster traversals of the design space of current complex SoC and embedded systems designs just as their complexity increases. To facilitate that designers are increasingly moving their exploration methodologies from RTL to system level. This, coupled with the need for a tighter integration between hardware and software earlier in the design cycle, has lead to emergence of mixed-level methodologies, such as SystemC, that allow for easier hardware/software codesign. In this paper, we describe a framework for the development of transformations aimed at restructuring both RTL and system-level SystemC models. We have chosen Petri nets, a well known mathematical model for concurrent systems, as our underlying formal representation. By balancing their expressive power and theoretical results transformations aimed at improving a wide range of metrics can be developed. To that effect we present the design and implementation of a semantics preserving reduction-based transformation that we have developed in previous work. Our experiments show that the resulting transformed SystemC models have indeed improved simulation performance over the original ones which often translates into designers being able to cover larger areas of the design space in the same amount of time.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"01 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130241791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Suppression of Redundant Operations in Reverse Compiled Code Using Global Dataflow Analysis 利用全局数据流分析抑制反编译代码中的冗余操作
Software and Compilers for Embedded Systems Pub Date : 2004-09-02 DOI: 10.1007/978-3-540-30113-4_8
A. Johnstone, E. Scott
{"title":"Suppression of Redundant Operations in Reverse Compiled Code Using Global Dataflow Analysis","authors":"A. Johnstone, E. Scott","doi":"10.1007/978-3-540-30113-4_8","DOIUrl":"https://doi.org/10.1007/978-3-540-30113-4_8","url":null,"abstract":"","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125794529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Framework for Architectural Description of Embedded System 嵌入式系统体系结构描述框架
Software and Compilers for Embedded Systems Pub Date : 2004-09-02 DOI: 10.1007/978-3-540-30113-4_2
D. C. Peixoto, D. Silva
{"title":"A Framework for Architectural Description of Embedded System","authors":"D. C. Peixoto, D. Silva","doi":"10.1007/978-3-540-30113-4_2","DOIUrl":"https://doi.org/10.1007/978-3-540-30113-4_2","url":null,"abstract":"","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"45 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129753445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units 使用粗粒度特定于应用程序的功能单元自动定制VLIW体系结构
Software and Compilers for Embedded Systems Pub Date : 2004-09-02 DOI: 10.1007/978-3-540-30113-4_3
Diviya Jain, Anshul Kumar, L. Pozzi, P. Ienne
{"title":"Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units","authors":"Diviya Jain, Anshul Kumar, L. Pozzi, P. Ienne","doi":"10.1007/978-3-540-30113-4_3","DOIUrl":"https://doi.org/10.1007/978-3-540-30113-4_3","url":null,"abstract":"","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126824221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications 一个用于数据密集型应用程序数据管理的自动化c++代码和数据分区框架
Software and Compilers for Embedded Systems Pub Date : 2004-09-02 DOI: 10.1007/978-3-540-30113-4_10
A. Milidonis, G. Dimitroulakos, M. D. Galanis, G. Theodoridis, C. Goutis, F. Catthoor
{"title":"An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications","authors":"A. Milidonis, G. Dimitroulakos, M. D. Galanis, G. Theodoridis, C. Goutis, F. Catthoor","doi":"10.1007/978-3-540-30113-4_10","DOIUrl":"https://doi.org/10.1007/978-3-540-30113-4_10","url":null,"abstract":"","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129586778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Predictable Embedded Multiprocessor System Design 可预测嵌入式多处理器系统设计
Software and Compilers for Embedded Systems Pub Date : 2004-09-02 DOI: 10.1007/978-3-540-30113-4_7
M. Bekooij, Orlando Moreira, P. Poplavko, B. Mesman, M. Pastrnak, J. V. Meerbergen
{"title":"Predictable Embedded Multiprocessor System Design","authors":"M. Bekooij, Orlando Moreira, P. Poplavko, B. Mesman, M. Pastrnak, J. V. Meerbergen","doi":"10.1007/978-3-540-30113-4_7","DOIUrl":"https://doi.org/10.1007/978-3-540-30113-4_7","url":null,"abstract":"","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132149395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 72
Integrated Intra- and Inter-task Cache Analysis for Preemptive Multi-tasking Real-Time Systems 抢占式多任务实时系统的任务内和任务间集成缓存分析
Software and Compilers for Embedded Systems Pub Date : 2004-09-02 DOI: 10.1007/978-3-540-30113-4_14
Yudong Tan, V. Mooney
{"title":"Integrated Intra- and Inter-task Cache Analysis for Preemptive Multi-tasking Real-Time Systems","authors":"Yudong Tan, V. Mooney","doi":"10.1007/978-3-540-30113-4_14","DOIUrl":"https://doi.org/10.1007/978-3-540-30113-4_14","url":null,"abstract":"","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134360395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
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