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Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000最新文献

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An approach to support a single service provider address image for wide area networks environment 一种在广域网环境下支持单个服务提供商地址映像的方法
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873602
J. Abawajy
{"title":"An approach to support a single service provider address image for wide area networks environment","authors":"J. Abawajy","doi":"10.1109/PCEE.2000.873602","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873602","url":null,"abstract":"Request dispatching mechanism is at the heart of any cluster-computing environment. The goal is to support a single service provider address image for a given cluster of workstations. That is to say a given cluster publicises a single IP address and client requests are addressed to that IP address. This means, from the client's viewpoint, there are no nodes in the cluster, only services and the network names through which they are accessible. As a result, the cluster becomes a single virtual node. We propose a simple and elegant scheme for making the cluster transparent to clients outside the cluster such that the clients can interact with the cluster as if it were a single high-performance and highly available resource.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127861295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
C++2MPI: a software tool for automatically generating MPI datatypes from C++ classes c++ 2MPI:一个从c++类自动生成MPI数据类型的软件工具
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873593
R. Hillson, M. Iglewski
{"title":"C++2MPI: a software tool for automatically generating MPI datatypes from C++ classes","authors":"R. Hillson, M. Iglewski","doi":"10.1109/PCEE.2000.873593","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873593","url":null,"abstract":"The Message Passing Interface I.I (MPI I.I) standard defines a library of message-passing functions for parallel and distributed computing. We have developed a new software tool called C++2MPI which can automatically generate MPI derived datatypes for a specified C++ class. C++2MPI can generate data types for derived classes, for partially and fully-specialized templated classes, and for classes with private data members. Given one or more user-provided classes as input, C++2MPI generates, compiles and archives a function for creating the MPI derived datatype. When the generated function is executed, it builds the derived MPI datatype if the datatype does not already exist, and returns the value of an MPI handle for referencing the datatype. PGMT (Processing Graph Method Tool) is a set of application program interfaces for porting the Processing Graph Method (PGM), a parallel programming method, to diverse networks of processors. C++2MPI was developed as a component of PGMT, but can be used as a stand-alone tool.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121294316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Sequential and distributed simulations using Java threads 使用Java线程的顺序和分布式模拟
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873636
M. Azizi, E. Aboulhamid, S. Tahar
{"title":"Sequential and distributed simulations using Java threads","authors":"M. Azizi, E. Aboulhamid, S. Tahar","doi":"10.1109/PCEE.2000.873636","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873636","url":null,"abstract":"We demonstrate an implementation methodology of sequential and distributed simulations using Java programming: two specific algorithms based on Java threads (single-channel and multi-channel algorithms) are proposed. From this point of view, the events are timely ordered into events lists and controlled by threads with respect to clock cycles. Each thread possesses an event list. The threads are globally timed in the sequential case by one clock, meanwhile in the distributed case they are locally clocked. The main application that is targeted by this work is the simulation of hardware/software systems, where different components are described by threads and obey a multi-clocked system.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126693992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reduction of waiting time in retrieving images utilizing image directories with sketched image as key 利用以草图图像为关键的图像目录减少检索图像的等待时间
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873614
Kayo Suzuki, M. Nagao, H. Ikeda
{"title":"Reduction of waiting time in retrieving images utilizing image directories with sketched image as key","authors":"Kayo Suzuki, M. Nagao, H. Ikeda","doi":"10.1109/PCEE.2000.873614","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873614","url":null,"abstract":"The image retrieval from the distributed image servers using a sketched image as a key was confirmed to be superior to that using keywords. In accordance with experimental and analytical studies, the total processing time of the image retrieval using a sketched image was much shorter than that of the image retrieval using keywords, and the total volume of data required for the image retrieval using a sketched image was much smaller than that for the image retrieval using keywords. On the image retrieval using a sketched image, the processing time was found to be reduced to one half of that in the conventional system when the image directories were installed in the new system. A mathematical model to derive the waiting time W from the processing time P was obtained as W=/spl lambda/P/sup 2//(1-/spl lambda/P), where /spl lambda/ is the rate of occurrence of the requests for the image retrieval. The calculated values were confirmed to agree with experimental data. Based on the studies, a high-speed image retrieval system was constructed using an image directory. Based on the experimental studies, the increases in success rate, reduction of processing time, total volume of data transmitted through the communication lines, and waiting time are theoretically derived to define the characteristics of the image database systems constructed using image directories.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115380060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
"Connection by communication" paradigm for dynamically reconfigurable multi-processor systems 动态可重构多处理器系统的“通信连接”范式
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873605
M. Tudruj
{"title":"\"Connection by communication\" paradigm for dynamically reconfigurable multi-processor systems","authors":"M. Tudruj","doi":"10.1109/PCEE.2000.873605","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873605","url":null,"abstract":"The paper presents a paradigm for inter-processor connection control in message passing parallel systems. The paradigm is bused on permanent inter-processor connections created under centralized control as a residual effect of data communications. It enables creation of temporal infrastructure of permanent interprocessor connections which is next used for dynamic mapping of execution of communication instructions. The proposed paradigm assumes co-existence of four types of connections which correspond to the basic communication models: packet switching and circuit switching in the synchronous and asynchronous versions. The corresponding system architectural features are discussed including structures of system components and connection setting principles for different communication models.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120944696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Concurrent implementation of linear and nonlinear programming 并行实现线性和非线性规划
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873598
A. Jordan, P. Prokopow
{"title":"Concurrent implementation of linear and nonlinear programming","authors":"A. Jordan, P. Prokopow","doi":"10.1109/PCEE.2000.873598","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873598","url":null,"abstract":"This paper presents the results of an example of a single-criterion problem which can be a link to a bigger decision making chain. Load balancing is the key issue for high performance of a parallel implementation of the problem. Due to its importance, load balancing is a well-studied problem in parallel and distributed systems in general. We would like to present three strategies that significantly reduce the runtime.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132906644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-level synthesis system (HLDESA) for processor arrays 处理器阵列高级综合系统(HLDESA)
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873608
R. Merker
{"title":"High-level synthesis system (HLDESA) for processor arrays","authors":"R. Merker","doi":"10.1109/PCEE.2000.873608","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873608","url":null,"abstract":"An approach to high-level synthesis of processor arrays is presented. In particular we describe methods and tools of the system HLDESA for processor array design which include resource constraints. Two major groups of resource constraints are considered: implementation constraints such as area and performance constraints to meet desired properties of the array as well as interface constraints such as communication constraints to ensure that the array can be embedded in a given environment. For integrating these two constraint types in the design process of processor arrays several optimization problems are described, and the method of iterative co-partitioning is presented.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124581785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Implementation of an adaptive reconfigurable group organized (ARGO) parallel architecture 一种自适应可重构组组织(ARGO)并行结构的实现
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873619
L. Szajek, L. Kirischian
{"title":"Implementation of an adaptive reconfigurable group organized (ARGO) parallel architecture","authors":"L. Szajek, L. Kirischian","doi":"10.1109/PCEE.2000.873619","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873619","url":null,"abstract":"The purpose of this paper is to demonstrate the implementation of an adaptable parallel architecture capable of system to task adaptation. The system implementation was based on XILINX FPGA devices. The adaptation was achieved by reconfiguring FPGAs to correspond to the task data flow graph. Scaling system resources and interconnecting them with a use of a virtual bus created clusters called group processors (GP). Each group processor operated as a fixed architecture system for the duration of the task. By developing custom macro operations such as vector processing units a speedup of as much as thirty times was obtained through hardware support and careful architecture selection. By developing multiple instances of macro-operations and combining them in GPs allowed efficient parallel processing.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114879815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Using Jini for high-performance network computing 使用Jini进行高性能网络计算
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873637
Q. Mahmoud
{"title":"Using Jini for high-performance network computing","authors":"Q. Mahmoud","doi":"10.1109/PCEE.2000.873637","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873637","url":null,"abstract":"Jini, which is based on Java, is a service-based system featuring automatic discovery of the network and its resources. It provides fault tolerance, distributed events and transaction mechanisms. This paper starts by giving a brief overview of Jini and highlights the features that can be effectively used for network computing. It describes how Jini attributes can be used in describing and searching for network computing services. A system for high performance network computing is then described.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121586792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Distributed hierarchical workstation cluster co-ordination scheme 分布式分层工作站集群协调方案
Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 Pub Date : 2000-08-27 DOI: 10.1109/PCEE.2000.873612
J. Abawajy, S. Dandamudi
{"title":"Distributed hierarchical workstation cluster co-ordination scheme","authors":"J. Abawajy, S. Dandamudi","doi":"10.1109/PCEE.2000.873612","DOIUrl":"https://doi.org/10.1109/PCEE.2000.873612","url":null,"abstract":"When a set of geographically distributed autonomous clusters of workstations are combined into a single large-scale virtual distributed system, a control mechanism for coordinating the activities of the combined system for effective utilisation of the resources is indispensable. This paper presents a co-ordination mechanism suitable for scheduling and distributing services across the host of such large-scale virtual distributed systems. The proposed scheme is scalable and reliable. Also, it combines both centralised and decentralised co-ordination mechanisms while eliminating/minimising their drawbacks.","PeriodicalId":369394,"journal":{"name":"Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127736864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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