2008 14th IEEE Pacific Rim International Symposium on Dependable Computing最新文献_第3页

A Peer-to-Peer Filter-Based Algorithm for Internal Clock Synchronization in Presence of Corrupted Processes 一种基于点对点滤波器的故障进程内部时钟同步算法

2008 14th IEEE Pacific Rim International Symposium on Dependable Computing Pub Date : 2008-12-15 DOI: 10.1109/PRDC.2008.38

R. Baldoni, M. Platania, Leonardo Querzoni, S. Scipioni

{"title":"A Peer-to-Peer Filter-Based Algorithm for Internal Clock Synchronization in Presence of Corrupted Processes","authors":"R. Baldoni, M. Platania, Leonardo Querzoni, S. Scipioni","doi":"10.1109/PRDC.2008.38","DOIUrl":"https://doi.org/10.1109/PRDC.2008.38","url":null,"abstract":"This paper proposes an internal clock synchronization algorithm for very large number of processes that is able to (i) self-synchronize their local clocks without any central control and (ii) resist to attacks of an adversary whose aim is to put out-of-synchronization as many correct processes as possible. To cope with scale the algorithm utilizes the gossip-based paradigm where each process has a limited view of the system, while to resist to attacks the algorithm employs a filtering mechanism based on the notion of ¿-trimmed mean to filter out out-of-range clock values. The algorithm shows nice convergence in presence of networks errors and in absence of the adversary. When the adversary takes control of some of the processes in the system, we define two goals for the adversary, actually two predicates, to measure the strength of the attack. The first one captures the percentage of time in which at least one correct is out of synchronization and the second one when all correct processes are out of synchronization. The paper presents an extensive simulation study showing under which conditions (in terms of number of corrupted processes and size of local views) these two goals can be achieved by the adversary. Interestingly, these results can be exploited by applications that can tolerate either a certain time in which some correct process is non-synchronized or a certain percentage of correct processes that is non-synchronized.","PeriodicalId":369064,"journal":{"name":"2008 14th IEEE Pacific Rim International Symposium on Dependable Computing","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115270630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Flexible Heterogeneous Strict Quorum-Based Dynamic Data Replication Schemes 灵活的异构严格基于仲裁的动态数据复制方案

2008 14th IEEE Pacific Rim International Symposium on Dependable Computing Pub Date : 2008-12-15 DOI: 10.1109/PRDC.2008.49

C. Storm, Timo Warns, Oliver E. Theel

引用次数: 4

Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy 基于双核和三核冗余的芯片多处理器瞬态容错

2008 14th IEEE Pacific Rim International Symposium on Dependable Computing Pub Date : 2008-12-15 DOI: 10.1109/PRDC.2008.40

Rui Gong, Kui Dai, Zhiying Wang

{"title":"Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy","authors":"Rui Gong, Kui Dai, Zhiying Wang","doi":"10.1109/PRDC.2008.40","DOIUrl":"https://doi.org/10.1109/PRDC.2008.40","url":null,"abstract":"To address the increasing susceptibility of microprocessors to transient faults, many techniques have been proposed to exploit the core redundancy of chip multiprocessors (CMPs). But the inter-core communications become critical in these core redundancy based techniques. To reduce the inter-core communication bandwidth demand, two new approaches, dual core redundancy (DCR) and triple core redundancy (TCR), are proposed for fault tolerance in this paper. In DCR, only store instructions are compared before commit, so that the bandwidth demand can be largely reduced. And the fault recovery is achieved by context saving and recovery. While TCR applies triple modular redundancy (TMR) in the core level to efficiently exploit the core resources of CMPs for transient fault masking. In TCR, only the results of store instructions are compared to detect transient fault and reduce the inter-core communication bandwidth demand. Once detecting a single event upset (SEU), TCR can be reconfigured to execute with the two uncorrupted cores for fault detection.The experimental results demonstrate that compared to traditional transient fault recovery scheme CRTR, both DCR and TCR efficiently reduce inter-core bandwidth demand. DCR achieves transient fault recovery with reasonable performance overhead caused by context saving. TCR occupies more core resources and has the lowest performance overhead during normal execution.","PeriodicalId":369064,"journal":{"name":"2008 14th IEEE Pacific Rim International Symposium on Dependable Computing","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115231748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor 一种容错嵌入式微处理器的主指令和冗余指令的轮流提取

2008 14th IEEE Pacific Rim International Symposium on Dependable Computing Pub Date : 2008-12-15 DOI: 10.1109/PRDC.2008.11

Shijian Zhang, Weiwu Hu

{"title":"Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor","authors":"Shijian Zhang, Weiwu Hu","doi":"10.1109/PRDC.2008.11","DOIUrl":"https://doi.org/10.1109/PRDC.2008.11","url":null,"abstract":"With the development of semiconductor technology, microprocessors become more and more susceptible to transient faults. Some proposed schemes support redundant execution of a program in a superscalar processor for fault tolerance. However, they require a huge queue to accommodate interim states, which enlarge the hardware cost significantly. This paper analyzes the effect of halving a processor¿s instruction fetch bandwidth on a program¿s performance. We find that the performance degradation resulted from halving instruction fetch bandwidth declines when instruction latency is lengthened, branch prediction accuracy deteriorates or cache miss rate increases. Since an embedded microprocessor is characterized by long instruction latency, high branch misprediction rate and cache miss rate, a fault-tolerant scheme is proposed, in which two threads fetch instructions in turn and execute in the same processor core simultaneously without any extra queue. The simulation results from eight embedded applications show that performance penalty of our solution ranges from 6.5% to 30.1%, with an average of 22.5%, which is lower than that of the other proposed schemes. The experiment also indicates that our scheme can effectively detect faults occurring in the entire pipeline with short fault detection latency and minimal hardware cost. It is well suited for our solution to realize a reliable embedded microprocessor.","PeriodicalId":369064,"journal":{"name":"2008 14th IEEE Pacific Rim International Symposium on Dependable Computing","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122388407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

VTV - A Voting Strategy for Real-Time Systems VTV -实时系统的投票策略

2008 14th IEEE Pacific Rim International Symposium on Dependable Computing Pub Date : 2008-12-15 DOI: 10.1109/PRDC.2008.28

Hüseyin Aysan, S. Punnekkat, R. Dobrin

引用次数: 11

A Study of Modified Testing-Based Fault Localization Method 改进的基于测试的故障定位方法研究

2008 14th IEEE Pacific Rim International Symposium on Dependable Computing Pub Date : 2008-12-15 DOI: 10.1109/PRDC.2008.34

Yu-Min Chung, Chin-Yu Huang, Yu-Chi Huang

{"title":"A Study of Modified Testing-Based Fault Localization Method","authors":"Yu-Min Chung, Chin-Yu Huang, Yu-Chi Huang","doi":"10.1109/PRDC.2008.34","DOIUrl":"https://doi.org/10.1109/PRDC.2008.34","url":null,"abstract":"In software development and maintenance, locating faults is generally a complex and time-consuming process. In order to effectively identify the locations of program faults, several approaches have been proposed. Similarity-aware fault localization (SAFL) is a testing-based fault localization method that utilizes testing information to calculate the suspicion probability of each statement. Dicing is also another method that we have used. In this paper, our proposed method focuses on predicates and their influence, instead of on statements in traditional SAFL. In our method, fuzzy theory, matrix calculating, and some probability are used. Our method detects the importance of each predicate and then provides more test data for programmers to analyze the fault locations. Furthermore, programmers will also gain some important information about the program in order to maintain their program accordingly. In order to speed up the efficiency, we also simplified the program. We performed an experimental study for several programs, together with another two testing-based fault localization (TBFL) approaches. These three methods were discussed in terms of different criteria such as line of code and suspicious code coverage. The experimental results show that the proposed method from our study can decrease the number of codes which have more probability of suspicion than real bugs.","PeriodicalId":369064,"journal":{"name":"2008 14th IEEE Pacific Rim International Symposium on Dependable Computing","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134492057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Efficient Dynamic Indexing Methods for Communication-Induced Checkpointing Protocols 通信诱导检查点协议的高效动态索引方法

2008 14th IEEE Pacific Rim International Symposium on Dependable Computing Pub Date : 2008-12-15 DOI: 10.1109/PRDC.2008.32

Jichiang Tsai, Wu-Hong Chen, Che-Cheng Chang

引用次数: 0

Reliability Quantification of the Tree Structure Based Distributed System 基于树形结构的分布式系统可靠性量化

2008 14th IEEE Pacific Rim International Symposium on Dependable Computing Pub Date : 2008-12-15 DOI: 10.1109/PRDC.2008.55

Dian-fu Ma, Min Liu, Yongwang Zhao, Dou Sun

引用次数: 0

Effect of Intrusion Detection on Failure Time of Mission-Oriented Mobile Group Systems in Mobile Ad Hoc Networks 入侵检测对移动Ad Hoc网络中面向任务的移动群系统故障时间的影响

2008 14th IEEE Pacific Rim International Symposium on Dependable Computing Pub Date : 2008-12-15 DOI: 10.1109/PRDC.2008.15

Jin-Hee Cho, I. Chen, Phu-Gui Feng

引用次数: 4

On the Complexity of a Self-Stabilizing Spanning Tree Algorithm for Large Scale Systems 大型系统自稳定生成树算法的复杂度

2008 14th IEEE Pacific Rim International Symposium on Dependable Computing Pub Date : 2008-12-15 DOI: 10.1109/PRDC.2008.36

J. Clément, T. Hérault, Stéphane Messika, O. Peres

引用次数: 4