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37th International Symposium on Multiple-Valued Logic (ISMVL'07)最新文献

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A Complete Resolution Calculus for Signed Max-SAT 符号Max-SAT的完全解析演算
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.2
C. Ansótegui, Maria Luisa Bonet, Jordi Levy, F. Manyà
{"title":"A Complete Resolution Calculus for Signed Max-SAT","authors":"C. Ansótegui, Maria Luisa Bonet, Jordi Levy, F. Manyà","doi":"10.1109/ISMVL.2007.2","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.2","url":null,"abstract":"We define a resolution-style rule for solving the Max-SAT problem of Signed CNF formulas (Signed Max-SAT) and prove that our rule provides a complete calculus for that problem. From the completeness proof we derive an original exact algorithm for solving Signed Max-SAT Finally, we present some connections between our approach and the work done in the Weighted CSP community.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131441927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions 四态磁随机存取存储器和基于钴胺的磁隧道结的三元内容可寻址存储器
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.25
T. Uemura, T. Marukame, K. Matsuda, Masafumi Yamamoto
{"title":"Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions","authors":"T. Uemura, T. Marukame, K. Matsuda, Masafumi Yamamoto","doi":"10.1109/ISMVL.2007.25","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.25","url":null,"abstract":"A four-state magnetic random access memory (MRAM) and ternary content addressable memory (TCAM) were developed using epitaxial Co50Fe50/MgO/Co50Fe50 magnetic tunnel junctions with a tunnel magnetoresistance (TMR) ratio of 145% at room temperature (RT). Four remanent magnetization states in the single-crystalline CoS0FeS0 electrode, due to the cubic anisotropy with easy axes of the (110) directions, result in four possible angular-dependent TMRs, each separated by more than 20% at RT. Analysis of the asteroid curve for Co50Fe50 indicated that the magnetic field along 22.5deg from the (110) directions made it possible to change the magnetization direction of the selected cell without disturbing those of the half-selected cells. The proposed non-volatile TCAM cell reduced the device count to 5, a value 1/3 compared to the conventional CMOS-based TCAMs.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131587131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
The Rough Powerset Monad Rough Powerset Monad
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.55
P. Eklund, María Ángeles Galán García
{"title":"The Rough Powerset Monad","authors":"P. Eklund, María Ángeles Galán García","doi":"10.1109/ISMVL.2007.55","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.55","url":null,"abstract":"Rough sets provide a good environment to deal with vagueness and uncertainty situations. In this paper we show how monads can be used to generalize and interpret rough situations. In particular, the partially ordered ordinary power set monad turns out to contain sufficient structure in order to provide rough set operations.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116454733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation 基于冗余多值顺序逻辑运算的通用VLSI
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.58
Tasuku Ito, M. Kameyama
{"title":"Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation","authors":"Tasuku Ito, M. Kameyama","doi":"10.1109/ISMVL.2007.58","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.58","url":null,"abstract":"In the next-generation VLSI, it is desired to achieve ultimate flexibility and a high-performance low-power operation equivalent to that of a full-custom VLSI. In this paper, a reconfigurable VLSI which realizes a high-performance sequential logic circuit based on a bit-serial operation is proposed. A universal sequential logic module (USLM) suitable for local data transfer in a programmed sequential logic circuit is presented. A redundant multiple-valued sequential logic operation is also proposed, where linear summation of time-by-time adjacent bits is fully utilized to increase the input/output throughput of a sequential logic circuit. Moreover, packet data transfer scheme is introduced to make programmable interconnection possible in the bit-serial data transfer between cells composed of the multiple USLMs.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115472645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On the Axiomatization of Generalized Entropic Metrics 关于广义熵度量的公理化
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ismvl.2007.40
D. Simovici
{"title":"On the Axiomatization of Generalized Entropic Metrics","authors":"D. Simovici","doi":"10.1109/ismvl.2007.40","DOIUrl":"https://doi.org/10.1109/ismvl.2007.40","url":null,"abstract":"Starting from an axiomatization of a generalization of Shannon entropy we introduce a set of axioms for a parametric family of distances over sets of partitions of finite sets. This family includes some well-known metrics used in data mining and in the study of finite functions.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121738434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluation and Comparison of Threshold Logic Gates 阈值逻辑门的评估与比较
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.18
Vasilios Lirigis, E. Dubrova
{"title":"Evaluation and Comparison of Threshold Logic Gates","authors":"Vasilios Lirigis, E. Dubrova","doi":"10.1109/ISMVL.2007.18","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.18","url":null,"abstract":"The threshold logic has a long history of more than 60 years. Many implementations have been proposed during the last decades. In this paper, we make a survey of most interesting implementations of capacitive, conductance/current and differential threshold logic gates. Using the Cadence Virtuosocopy Mixed Signal Front to Back, we evaluate and compare these implementations in terms of speed, area and power consumption for basic circuits.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123118273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Reading the Sampling Theorem in Multiple-Valued Logic: A Journey from the (Shannong) Sampling Theorem to the Shannon Decomposition Rule 解读多值逻辑中的抽样定理:从(山农)抽样定理到香农分解规则的历程
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.48
R. Stankovic, J. Astola
{"title":"Reading the Sampling Theorem in Multiple-Valued Logic: A Journey from the (Shannong) Sampling Theorem to the Shannon Decomposition Rule","authors":"R. Stankovic, J. Astola","doi":"10.1109/ISMVL.2007.48","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.48","url":null,"abstract":"Signals described by functions of continuous and discrete variables can be uniformly studied in a group theoretic framework. This paper presents a consideration which shows that in the case of multiple-valued (MV) functions, the notion of bandwidth relates to the concept of essential variables. Sampling conditions convert into requirements for periodicity and regularity in the truth-vectors of MV functions. Due to that, by starting from the sampling theorem, we derive generalized Shannon decomposition rules for MV functions that include the classical Shannon decomposition rule in binary-valued logic as a particular case. It follows from these considerations that the sampling theorem provides a regular way for the decomposition of a MV function into subfunctions of smaller numbers of variables. In circuit synthesis, this allows decomposition of a network to realize a function into subnetworks realizing subfunctions depending on subsets of variables, where the cardinality of the subsets is determined by the bandwidth selected. As there are no convergence problems, the sampling theorem for discrete functions can be formulated in terms of a class of Fourier-like transforms with certain properties provided. Due to that, different decompositions of a given function can be determined by selecting various Fourier-like transforms.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133312813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A Note on Possible Applications of Fourier Representations in Circuit Design over Reprogrammable Technological Platforms 傅立叶表示在可重编程技术平台上电路设计中的可能应用
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.4
R. Stankovic, J. Astola
{"title":"A Note on Possible Applications of Fourier Representations in Circuit Design over Reprogrammable Technological Platforms","authors":"R. Stankovic, J. Astola","doi":"10.1109/ISMVL.2007.4","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.4","url":null,"abstract":"There are two basic tasks in exploiting field programmable gate arrays (FPGAs). First is to decompose a problem to be realized over a collection of basic blocks. The second is to efficiently exploit all the resources available, to be able to perform more on a single chip. In this paper, we suggest possible solutions to these tasks by exploiting spectral methods to represent logic functions to be realized. We show that the decomposition inherent in FFT-like algorithms can be used to decompose a discrete function into subfunctions realizable separately. These sub- functions can be assembled into required functionality by digital signal processors (DSPs) that are already included in some FPGAs. Due to that, the design of larger amounts of logic can be performed over resources that may often remain inefficiently exploited even when resources dedicated to realize logic are exhausted on a given chip.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122492311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme 采用单相信令方案的异步点对点单工/双工兼容通信系统
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.8
Tomohiro Takahashi, K. Mizusawa, T. Hanyu
{"title":"Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme","authors":"Tomohiro Takahashi, K. Mizusawa, T. Hanyu","doi":"10.1109/ISMVL.2007.8","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.8","url":null,"abstract":"This paper presents an asynchronous peer-to-peer simplex/duplex-compatible communication system. The channels are based on a 1-phase signaling scheme that has the simultaneous handshaking and delay insensitivity, which achieves not only high-speed but also robust communication to variations of wire delays. A transmission is controllable by adding a mode-detection channel that observes the mutual states in both ends. Since current sources are appropriately controlled depending on mutual states, the power dissipation can be greatly reduced when both ends are on standby. Moreover, both simplex and duplex communication can be realized by sharing a common circuit except a signal-level conversion circuit. The proposed interface is implemented and evaluated using 0.18-mum CMOS, and its performance and efficiency are discussed.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124706284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Variable Reordering and Sifting for QMDD QMDD的可变重排序和筛选
37th International Symposium on Multiple-Valued Logic (ISMVL'07) Pub Date : 2007-05-13 DOI: 10.1109/ISMVL.2007.59
D. M. Miller, D. Y. Feinstein, Mitchell A. Thornton
{"title":"Variable Reordering and Sifting for QMDD","authors":"D. M. Miller, D. Y. Feinstein, Mitchell A. Thornton","doi":"10.1109/ISMVL.2007.59","DOIUrl":"https://doi.org/10.1109/ISMVL.2007.59","url":null,"abstract":"This paper considers variable reordering for quantum multiple-valued decision diagrams (QMDD) used to represent the matrices describing reversible and quantum gates and circuits. An efficient method for adjacent variable interchange is presented and this method is employed to implement sifting of QMDDs. Experimental results are presented showing the effectiveness of the proposed techniques.","PeriodicalId":368339,"journal":{"name":"37th International Symposium on Multiple-Valued Logic (ISMVL'07)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124147163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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