Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors最新文献_第4页

A linear array parallel image processor: SliM-II 线性阵列并行图像处理器SliM-II

Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 1997-07-14 DOI: 10.1109/ASAP.1997.606810

Hyunman Chang, S. Ong, M. Sunwoo

{"title":"A linear array parallel image processor: SliM-II","authors":"Hyunman Chang, S. Ong, M. Sunwoo","doi":"10.1109/ASAP.1997.606810","DOIUrl":"https://doi.org/10.1109/ASAP.1997.606810","url":null,"abstract":"This paper describes architectures and design of a general purpose parallel image processor chip called a SliM-II Image Processor. The chip has a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives 1.92 GIPS. SIiM-II can greatly reduce the inter-PE communication overhead, due to the idea of sliding that is overlapping inter-PE communication with computation. In contrast to existing array processors, each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simultaneously in an instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel load/store between the register file and on-chip memory as in DSP chips. The bandwidth of data I/O and inter-PE communication increases due to bit-parallel paths. We developed VHDL models and performed logic synthesis using the COMPASS/sup TM/ CAD tool. We used the COMPASS/sup TM/ 3.3 V 0.6 /spl mu/m standard cell library (v8r4.9.1). The total number of transistors is about 1.5 millions. The SliM-II chip is being fabricated at the LG Semiconductor Co,, Ltd. The performance estimation shows a significant improvement for algorithms requiring multiplications compared with existing array processors.","PeriodicalId":368315,"journal":{"name":"Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128123315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Realization of a nonlinear digital filter on a DSP array processor 非线性数字滤波器在DSP阵列处理器上的实现

Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 1997-07-14 DOI: 10.1109/ASAP.1997.606809

H. Kwan, E. Powers, E. Swartzlander

引用次数: 3

Low latency word serial CORDIC 低延迟字串行CORDIC

Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 1997-07-14 DOI: 10.1109/ASAP.1997.606819

J. Villalba, T. Lang

引用次数: 7

Mapping multirate dataflow to complex RT level hardware models 将多速率数据流映射到复杂的RT级硬件模型

Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 1997-07-14 DOI: 10.1109/ASAP.1997.606834

J. Horstmannshoff, Thorsten Grötker, H. Meyr

{"title":"Mapping multirate dataflow to complex RT level hardware models","authors":"J. Horstmannshoff, Thorsten Grötker, H. Meyr","doi":"10.1109/ASAP.1997.606834","DOIUrl":"https://doi.org/10.1109/ASAP.1997.606834","url":null,"abstract":"The design of digital signal processing systems typically consists of an algorithm development phase carried out at a behavioral level and the selection of an efficient hardware architecture for implementation. In order to speed up the joint optimization of algorithms and architectures, a fast path to implementation must be provided. This can be achieved efficiently by directly mapping the data flow specification of the system to an RTL target architecture by means of HDL code generation. For algorithm design, communication systems are most easily modeled using multirate data flow graphs in which no notion of time is maintained. HDL code generation introduces a cycle based timing model and maps the data flow models to RTL implementations, which are usually taken from a library. Due to the increase in ASIC design complexity, these building blocks reach a high level of functionality and have complex interfacing properties. Therefore, it becomes necessary to generate additional interfacing and controlling hardware to synthesize an operable system. In this paper, we present a new approach of mapping multirate dataflow graphs to complex RTL hardware models and derive algorithms to synthesize these high-level RTL building blocks into a complete operable system.","PeriodicalId":368315,"journal":{"name":"Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115952463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

A logical framework to prove properties of ALPHA programs 证明ALPHA程序性质的逻辑框架

Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 1997-07-14 DOI: 10.1109/ASAP.1997.606825

L. Bougé, D. Cachera

引用次数: 3

Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture RISC CPU在并行多媒体架构中作为嵌入式控制器的概念与设计

Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 1997-07-14 DOI: 10.1109/ASAP.1997.606846

S. Dogimont, M. Gumm, F. Mombers, D. Mlynek, A. Torielli

引用次数: 8

The processing graph method tool (PGMT) 加工图方法工具(PGMT)

Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 1997-07-14 DOI: 10.1109/ASAP.1997.606832

R. S. Stevens

{"title":"The processing graph method tool (PGMT)","authors":"R. S. Stevens","doi":"10.1109/ASAP.1997.606832","DOIUrl":"https://doi.org/10.1109/ASAP.1997.606832","url":null,"abstract":"To acquire stare-of-the-art hardware at reduced cost, the U.S. Navy is committed to buying commercial off the shelf (COTS) computer hardware. In this rapidly changing technological world, today's hardware will be obsolete tomorrow. The Navy's complex problems often require more computational power than can be delivered by a single serial processor. The solution lies in distributed processing. However, distributed processors tend to have architecture specific languages, requiring an expensive and time-consuming manual rewrite of application software as new technology and new machines become available. The processing graph method (PGM), developed at the Naval Research Laboratory (NRL) in Washington, DC, is an architecture independent method for specifying application software for distributed architectures. Its model of computation is reconfigurable dynamic data flow: dynamic because the amount of data consumed and produced by an actor may vary from one firing to another; and reconfigurable, because a graph may be disassembled and reassembled. PGM was implemented on the Navy Standard Signal Processor (AN/UYS-2), and on VAX and Sun workstations. The PGMT project at NRL is developing a tool set that will facilitate the implementation of PGM on a given distributed architecture at relatively low cost. We describe the major features PGM and discuss the PGMT project.","PeriodicalId":368315,"journal":{"name":"Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116956126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A modular element for shared buffer ATM switch fabrics 用于共享缓冲ATM交换结构的模块化元件

Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 1997-07-14 DOI: 10.1109/ASAP.1997.606848

Mike Parks

引用次数: 0

A methodology for user-oriented scalability analysis 面向用户的可伸缩性分析方法

Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 1997-07-14 DOI: 10.1109/ASAP.1997.606836

D. Royo, M. Valero-García, Antonio González, Carme Mari

引用次数: 0

A multiprocessor system for real time high resolution image correlation 一个实时高分辨率图像相关的多处理器系统

Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 1997-07-14 DOI: 10.1109/ASAP.1997.606843

M. Cavadini, M. Wosnitza, M. Thaler, G. Tröster

引用次数: 4