Proceedings of the 39th International Conference on Computer-Aided Design最新文献

CleaNN

Proceedings of the 39th International Conference on Computer-Aided Design Pub Date : 2020-11-02 DOI: 10.1145/3400302.3415671

Mojan Javaheripi, Mohammad Samragh, G. Fields, T. Javidi, F. Koushanfar

引用次数: 26

MobiLatice MobiLatice

Proceedings of the 39th International Conference on Computer-Aided Design Pub Date : 2020-11-02 DOI: 10.1145/3400302.3415666

Qilin Zheng, Xingchen Li, Zongwei Wang, Guangyu Sun, Yimao Cai, Ru Huang, Yiran Chen, H. Li

{"title":"MobiLatice","authors":"Qilin Zheng, Xingchen Li, Zongwei Wang, Guangyu Sun, Yimao Cai, Ru Huang, Yiran Chen, H. Li","doi":"10.1145/3400302.3415666","DOIUrl":"https://doi.org/10.1145/3400302.3415666","url":null,"abstract":"Nonvolatile Processing-In-Memory (NVPIM) architecture is a promising technology to enable energy-efficient inference of Deep Convolutional Neural Networks (DCNNs). One major advantage of NVPIM is that the vector dot-product operations can be completed efficiently by analog computing inside a Nonvolatile Memory (NVM) crossbar. However, its inference efficiency is severely downgraded when processing depth-wise convolution layers, which have been widely employed in many lightweight DCNNs. One major challenge is that the cell utilization is extreme low when mapping the depth-wise convolution layer to a crossbar. To overcome this problem, we propose a novel hybrid mode NVPIM architecture, namely, MobiLattice. With moderate hardware overhead, Mobi-Lattice enables both analog and digital mode operations on NVM crossbars. While conventional convolution layers are computed efficiently using the analog mode, the computation efficiency of depth-wise convolution layers are substantially improved using the digital mode by mitigating the redundant memory space in the NVM crossbars. Experimental results show that, compared to prior approaches where only the analog mode is supported by the NVPIM architecture, MobiLattice can speedup the processing of typical depth-wise DCNNs by 2 ~5× on average and up to 30× by combining with some extreme quantization schemes.","PeriodicalId":367868,"journal":{"name":"Proceedings of the 39th International Conference on Computer-Aided Design","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115732742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

PROS 优点

Proceedings of the 39th International Conference on Computer-Aided Design Pub Date : 2020-11-02 DOI: 10.1145/3400302.3415662

Jingsong Chen, Jian Kuang, Guowei Zhao, D. J. Huang, Evangeline F. Y. Young

引用次数: 9

CCCS 推动者

Proceedings of the 39th International Conference on Computer-Aided Design Pub Date : 2020-11-02 DOI: 10.1145/3400302.3415627

Fan Zhang, Miao Hu

引用次数: 9

ABACUS 算盘

Proceedings of the 39th International Conference on Computer-Aided Design Pub Date : 2020-11-02 DOI: 10.1145/3400302.3415673

Tianyu Wang, Wenbin Zhu, Qun Ma, Zhaoyan Shen, Z. Shao

{"title":"ABACUS","authors":"Tianyu Wang, Wenbin Zhu, Qun Ma, Zhaoyan Shen, Z. Shao","doi":"10.1145/3400302.3415673","DOIUrl":"https://doi.org/10.1145/3400302.3415673","url":null,"abstract":"DAG-based blockchain systems have been deployed to enable trustworthy peer-to-peer transactions for IoT devices. Unique address checking, as a key part of transaction generation for privacy and security protection in DAG-based blockchain systems, incurs big latency overhead and degrades system throughput. In this paper, we propose a Bloom-filter-based approach, called ABACUS to optimize the unique address checking process. We partition the large address space into multiple small subspaces and apply one Bloom filter to perform uniqueness checking for all addresses in a subspace. Specifically, we propose a two-level address space mechanism so as to strike a balance between the checking efficiency and the memory/storage space overhead of the Bloom filter design. A bucket-based scalable Bloom filter design is proposed to address the growth of used addresses and provide the checking latency guarantee with efficient I/O access through storing all sub-Bloom-filters together in one bucket. To further reduce disk I/Os, ABACUS incorporates an in-memory write buffer and a read-only cache. We have implemented ABACUS into IOTA, one of the most widely used DAG-based blockchain systems, and conducted a series of experiments on a private IOTA system. The experimental results show that ABACUS can significantly reduce the transaction generation time by up to four orders of magnitude while achieving up to 3X boost on the system throughput, compared with the original design.","PeriodicalId":367868,"journal":{"name":"Proceedings of the 39th International Conference on Computer-Aided Design","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124201802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

NeuroMAX NeuroMAX

Proceedings of the 39th International Conference on Computer-Aided Design Pub Date : 2020-11-02 DOI: 10.1145/3400302.3415638

Mahmood Azhar Qureshi, Arslan Munir

{"title":"NeuroMAX","authors":"Mahmood Azhar Qureshi, Arslan Munir","doi":"10.1145/3400302.3415638","DOIUrl":"https://doi.org/10.1145/3400302.3415638","url":null,"abstract":"Convolutional neural networks (CNNs) require high throughput hardware accelerators for real time applications owing to their huge computational cost. Most traditional CNN accelerators rely on single core, linear processing elements (PEs) in conjunction with 1D dataflows for accelerating convolution operations. This limits the maximum achievable ratio of peak throughput per PE count to unity. Most of the past works optimize their dataflows to attain close to a 100% hardware utilization to reach this ratio. In this paper, we introduce a high throughput, multi-threaded, log-based PE core. The designed core provides a 200% increase in peak throughput per PE count while only incurring a 6% increase in area overhead compared to a single, linear multiplier PE core with same output bit precision. We also present a 2D weight broadcast dataflow which exploits the multi-threaded nature of the PE cores to achieve a high hardware utilization per layer for various CNNs. The entire architecture, which we refer to as NeuroMAX, is implemented on Xilinx Zynq 7020 SoC at 200 MHz processing clock. Detailed analysis is performed on throughput, hardware utilization, area and power breakdown, and latency to show performance improvement compared to previous FPGA and ASIC designs.","PeriodicalId":367868,"journal":{"name":"Proceedings of the 39th International Conference on Computer-Aided Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114596686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Aadam

Proceedings of the 39th International Conference on Computer-Aided Design Pub Date : 2020-11-02 DOI: 10.1145/3400302.3415605

S. M. Ebrahimipour, B. Ghavami, Hamid Mousavi, Mohsen Raji, Zhenman Fang, Lesley Shannon

{"title":"Aadam","authors":"S. M. Ebrahimipour, B. Ghavami, Hamid Mousavi, Mohsen Raji, Zhenman Fang, Lesley Shannon","doi":"10.1145/3400302.3415605","DOIUrl":"https://doi.org/10.1145/3400302.3415605","url":null,"abstract":"With the CMOS technology scaling, transistor aging has become one major issue affecting circuit reliability and lifetime. There are two major classes of existing studies that model the aging effects in the circuit delay. One is at transistor-level, which is highly accurate but very slow. The other is at gate-level, which is faster but less accurate. Moreover, most prior studies only consider a limited subset or limited value ranges of aging factors. In this paper, we propose Aadam, a fast, accurate, and versatile aging-aware delay model for generic cell libraries. In Aadam, we first use transistor-level SPICE simulations to accurately characterize the delay degradation of each library cell under a versatile set of aging factors, including both physical parameters (i.e., initial threshold voltage and transistor width/length ratio) and operating conditions (i.e., working temperature, signal probability, input signal slew range, output load capacitance range, and projected lifetime). For each library cell, we then train a feed-forward neural network (FFNN) to learn the relation between the input aging factors and output cell delay degradation. Therefore, for a given input circuit and a given combination of aging factors, we can use the trained FFNNs to quickly and accurately infer the delay degradation for each gate in the circuit. Finally, to effectively estimate the aging-aware lifetime delay of large-scale circuits, we also integrate Aadam into a state-of-the-art static timing analysis tool called OpenTimer. Experimental results demonstrate that Aadam achieves fast estimation of the aging-induced delay with high accuracy close to transistor-level simulation.","PeriodicalId":367868,"journal":{"name":"Proceedings of the 39th International Conference on Computer-Aided Design","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124889768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Machine learning and hardware security: challenges and opportunities 机器学习和硬件安全:挑战与机遇

Proceedings of the 39th International Conference on Computer-Aided Design Pub Date : 2020-11-02 DOI: 10.1145/3400302.3416260

F. Regazzoni, S. Bhasin, Amir Ali Pour, Ihab Alshaer, Furkan Aydin, Aydin Aysu, V. Beroulle, Giorgio Di Natale, P. Franzon, D. Hély, N. Homma, Akira Ito, Dirmanto Jap, Priyank Kashyap, I. Polian, S. Potluri, Rei Ueno, E. Vatajelu, Ville Yli-Mäyry

引用次数: 4

GAMMA γ

Proceedings of the 39th International Conference on Computer-Aided Design Pub Date : 2020-11-02 DOI: 10.1145/3400302.3415639

Sheng-Chun Kao, T. Krishna

引用次数: 73

MLCache

Proceedings of the 39th International Conference on Computer-Aided Design Pub Date : 2020-11-02 DOI: 10.1145/3400302.3415652

Weiguang Liu, Jinhua Cui, Junwei Liu, L. Yang

{"title":"MLCache","authors":"Weiguang Liu, Jinhua Cui, Junwei Liu, L. Yang","doi":"10.1145/3400302.3415652","DOIUrl":"https://doi.org/10.1145/3400302.3415652","url":null,"abstract":"Non-volatile memory express (NVMe) solid-state drives (SSDs) have been widely adopted in emerging storage systems, which can provide multiple I/O queues and high-speed bus to maximize high data transfer rate. NVMe SSD use streams (also called “Multi-Queue”) to store related data in associated locations or for other performance enhancements. The on-board DRAM cache inside NVMe SSDs can efficiently reduce the disk accesses and extend the lifetime of SSDs, thus improving the overall efficiency of the storage systems. However, in previous studies, such SSD cache has been only used as a shared cache for all streams or a statically partitioned cache for each stream, which may seriously degrade the performance-per-stream and underutilize the valuable cache resources. In this paper, we present MLCache, a space-efficient shared cache management scheme for NVMe SSDs, which maximizes the write hit ratios, as well as enhances the SSD lifetime. We formulate cache space allocation as a machine learning problem. By learning the impact of reuse distance on cache allocation, we build a workload specific neural network model. At runtime, MLCache continuously monitors the reuse distance distribution for the neural network module to obtain space-efficient allocation decisions. Experimental results show MLCache improves the write hit ratio of the SSD by 24% compared to baseline, and achieves response time reduction by 13.36% when compared with baseline. MLCache is 96% similar to the ideal model.","PeriodicalId":367868,"journal":{"name":"Proceedings of the 39th International Conference on Computer-Aided Design","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122508896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1