2021 5th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)最新文献_第7页

Digital Image Watermarking Technique Using Arnold Transform and Lifting 基于阿诺德变换和提升的数字图像水印技术

2021 5th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) Pub Date : 2021-09-24 DOI: 10.1109/IEMENTech53263.2021.9614890

Pritom Adhikary, A. Phadikar, Himadri S. Mandal, Prasannita Singh

{"title":"Digital Image Watermarking Technique Using Arnold Transform and Lifting","authors":"Pritom Adhikary, A. Phadikar, Himadri S. Mandal, Prasannita Singh","doi":"10.1109/IEMENTech53263.2021.9614890","DOIUrl":"https://doi.org/10.1109/IEMENTech53263.2021.9614890","url":null,"abstract":"In this paper, we propose a digital image watermarking scheme using Arnold transform. To implement this, a scrambled binary image is embedded into the coefficient of host images via Lifting wavelet transform. Then inverse wavelet transform is applied to get the watermarked image. We have applied to watermark in the transform domain instead of the spatial domain. This is since in a spatial domain the pixels of the cover image is directly manipulated, in contrast with transform domain where the coefficient of pixels is modified after applying different transformation technique that ultimately increases imperceptibility of the scheme. Moreover, nowadays most of the images are compressed in wavelet domain like JPEG 2000. Another important feature of the proposed algorithm is the Arnold scrambling technique which increases the security of the scheme. It is difficult for the attacker to derive the original watermark as well as retrieve the cover image. The proposed digital watermarking system is tested over a large number of standard grayscale (512×512) benchmark images to provide good imperceptibility and robustness. In our case, we have seen that the proposed technique offers the average value of peak signal-to-noise ratio (PSNR), Structural Similarity Index (SSI) before decoding and after decoding are 49.93, 0.97, 51.72 and 0.976721 respectively. The experimental results show that the proposed scheme is robust against different types of attacks.","PeriodicalId":367069,"journal":{"name":"2021 5th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132645809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Compact Altered Current Starved CMOS VCO in 130 nm with Broad Linear Tuning and Ultra-Low Power Dissipation 具有宽线性调谐和超低功耗的130nm紧凑变电流饥渴CMOS压控振荡器

2021 5th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) Pub Date : 2021-09-24 DOI: 10.1109/IEMENTech53263.2021.9614913

Suhas D

引用次数: 0

High Directivity and High Gain Microstrip Patch Antenna for 5G Application with Defective and Suspended Ground Plane 高指向性高增益微带贴片天线在5G应用中的缺陷和悬地平面

2021 5th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) Pub Date : 2021-09-24 DOI: 10.1109/IEMENTech53263.2021.9614841

Ashwin Kumar Gondi, Aditya Dilip Jaiswal, S. Vignesh, D. Yadav

引用次数: 0

Novel Methodology to Validate DUTs Using Single Access Structure 使用单访问结构验证dut的新方法

2021 5th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) Pub Date : 2021-09-24 DOI: 10.1109/IEMENTech53263.2021.9614863

C. Pittala, J. Sravana, G. Ajitha, P. Saritha, Mohammad Khadir, V. Vijay, S. Venkateswarlu, Rajeev Ratna Vallabhuni

{"title":"Novel Methodology to Validate DUTs Using Single Access Structure","authors":"C. Pittala, J. Sravana, G. Ajitha, P. Saritha, Mohammad Khadir, V. Vijay, S. Venkateswarlu, Rajeev Ratna Vallabhuni","doi":"10.1109/IEMENTech53263.2021.9614863","DOIUrl":"https://doi.org/10.1109/IEMENTech53263.2021.9614863","url":null,"abstract":"Conventional shift-based scan chains have the drawback of peak power consumption which is reduced by the proposed single cycle access test structure for logic test. With the reduction of this power consumption the activity during shift and capture cycles have been achieved. In addition, more accurate circuit behavior can be achieved even at stuck-at and at-speed tests using the proposed methodology. Thereby it accomplishes close proximity to the functional mode during higher frequency operation tests. By using the proposed design minimum number of test cycles can be gained to the existed literature. It is observed that test cycles per net is below 1 for larger designs when tested for simple test pattern generator algorithm without test pattern compression. Has the advantage of autonomous of the plan estimate conjointly gives an extra on-chip investigating flag permeability for each enrols. It is in reverse congruous to the standard full check plans and with a minor improvement existing test design generators and test systems can be utilized conjointly talked about for the arrangement of including built-in self-test (BIST) and gigantic parallel check chains with the proposed plan. The design and implementation of single cycle access test structure for logic test is functionally verified using Vivado. The pre layout and post layout synthesis and its physical design are performed using cadence Genus and Innonus tools respectively, with the optimized area, power, and delay.","PeriodicalId":367069,"journal":{"name":"2021 5th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126620425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0