1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)最新文献

{"title":"Comparison sets: A useful partitioning of the space of floating point operand pairs","authors":"J. G. Kent","doi":"10.1109/ARITH.1975.6156991","DOIUrl":"https://doi.org/10.1109/ARITH.1975.6156991","url":null,"abstract":"In this paper the definition of comparison sets and a discussion of their usefulness are presented based on the research work reported in (14). In addition some new results concerning the distribution of floating point (FLP) operand pairs over comparison sets are given.","PeriodicalId":360742,"journal":{"name":"1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)","volume":"24 32","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120842101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Self-checking adder for large scale integration","authors":"A. Svoboda","doi":"10.1109/ARITH.1975.6157005","DOIUrl":"https://doi.org/10.1109/ARITH.1975.6157005","url":null,"abstract":"The testing of LSI chips is expensive and unsatisfactory. On the other hand there are cases (as in space ship computers) where a damaged chip must be localized and replaced. The use of self-checking chips seems to be one of several possible solutions of this problem. The theory of the structure of self-checking logical circuit is covered by literature at least at the fundamental form (see References). However, even when the design principles are supposed to be known, their application to the actual creation of a self-checking circuit of an average complexity is and will remain an art. The reason is quite simple and fundamental: optimization of design criteria (engineering qualifications, performance and physical properties of components of the circuits are entities possessing different physical dimensions — it is impossible to qualify, for instance, two circuits A, B designed for the same task by comparing their speeds and costs if A is faster than B but B is cheaper than A) will never be objective and independent of the talent or whim of the circuit designer. As an example of the design of a self-checking circuit we present here a binary adder (Full Adder) designed under the following considerations: 1: The adder is composed from gates (AND, 0R, NAND, N0R, …). 2: Two level design was chosen. 3. Ripple carry addition was accepted as sufficient simplification for the design experiment. 4. Only two classes of fault were considered: Stuck at ONE, Stuck at ZERO. 5. Any single fault in the circuit must be signalized either during the activity of the circuit (clock ON) or during a test fault injection (clock OFF). 6. The number of cases where a multiple fault remains undetected must be extremely low in comparison with all possible cases. To obtain an adder with all those requirements the following design idea is used: The adder's three bit input (X, Y, C) is transformed into an eight bit signal (S1, i = 0, 1, …, 7) by using ONE FROM EIGHT CODE. This signal, produced by the first level of the circuit, is then transformed by the second level of the circuit into the desired output signal (Z, G) by using four wires and TWO FROM FOUR CODE. Ten fault signals (Fig. 1) are derived from those two codes and checked at the proper state of the clock.","PeriodicalId":360742,"journal":{"name":"1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115485778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Formal systems of numerals","authors":"A. Gabrielian","doi":"10.1109/ARITH.1975.6156984","DOIUrl":"https://doi.org/10.1109/ARITH.1975.6156984","url":null,"abstract":"A new system of numerals is introduced for representing numbers in base 2N for N≤8. The new notation greatly simplifies arithmetical operations on numbers. For examples for, N=3(4) one obtains a notation for octal (hexadecimal) numbers in which one can perform addition and multiplication much more easily than in the standard notation. For N=8 one obtains a practical way of representing numbers to the base 256. A simplification of the decimal notation is also presented.","PeriodicalId":360742,"journal":{"name":"1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122390243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On combinational logic for sign detection in residue number systems","authors":"D. Banerji, Saroj Kaushik","doi":"10.1109/ARITH.1975.6156971","DOIUrl":"https://doi.org/10.1109/ARITH.1975.6156971","url":null,"abstract":"This paper is concerned with the algebraic sign detection of a number in a residue number system. The proposed solution is applicable only to nonredundant systems. The method utilizes a systematic decomposition of the sign function S that is based on some special properties of S. Starting with the canonical sum-of-products expression for S, we transform the expression to a form whose realization is simpler than the canonical form realization and, if possible, also simpler than the minimal sum-of-products realization. In some cases, the proposed method yields savings as high as 85% compared to the minimal sum-of-products realization for S.","PeriodicalId":360742,"journal":{"name":"1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128166676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Case study of the pipelined arithmetic unit for the TI Advanced Scientific Computer","authors":"Charles Stephenson","doi":"10.1109/ARITH.1975.6157003","DOIUrl":"https://doi.org/10.1109/ARITH.1975.6157003","url":null,"abstract":"Introduction Many scientific applications today require computers which are very fast and capable of processing large amounts of data. Some advances in scientific processing have been slowed due to the lack of supercomputer capabilities which are required primarily in the area of Central Processor speed and the availability of large amounts of high speed memory. Particularly in the fields of modeling and simulation, additional speed and memory capacity are desired to allow increased resolution of the experiment. Technological developments in such things as integrated circuits, multilayer printed circuit boards, memory speeds, and others have contributed to the ability of computer manufacturers to serve this market. In addition to these developments, however, large advances had to be realized from the standpoint of the basic computer architecture. The concept of pipelining has provided an answer to the large data execution rate required. Pipelined capabilities in the form of arithmetic units and special purpose functional units are included in machines such as the CEC7600, IBM 360/195, CDC STAR-100, etc.1,2 The Texas Instruments Advanced Scientific Computer (ASC) uses the pipeline concept throughout the Central Processor and carries the concept throughout the Central Processor and carries the concept further to include vector instructions in response to the high execution rates required.3","PeriodicalId":360742,"journal":{"name":"1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)","volume":"48 2-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133089335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The design of a Polymorphic Arithmetic Unit","authors":"A. L. Lang, B. Shriver","doi":"10.1109/ARITH.1975.6156997","DOIUrl":"https://doi.org/10.1109/ARITH.1975.6156997","url":null,"abstract":"This paper presents results which stem from a research effort concerned with the specification and design of arithmetic units which can execute nonstandard integer and floating-point arithmetic. An arithmetic unit is proposed whose characteristics are based on user specifications and subsequently is termed a Polymorphic Arithmetic Unit (PAU). The user binds the identity of the PAU by specifying the contents of various descriptors and semantic interpretation tables which the PAU accesses during its execution. This capability removes several of the restrictions found in commercially available arithmetic units and potentially assists in mak-ink mathematically software portable.","PeriodicalId":360742,"journal":{"name":"1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124633311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-speed zero-sum detection","authors":"A. Weinberger","doi":"10.1109/ARITH.1975.6157008","DOIUrl":"https://doi.org/10.1109/ARITH.1975.6157008","url":null,"abstract":"A common requirement accompanying high-speed parallel addition is the early detection that the sum is equal to zero. Normally, this condition is detected from the sum, generally at least two logic gate levels after the sum.","PeriodicalId":360742,"journal":{"name":"1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123040049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel multiply-by-three circuit","authors":"C. Foster, E. Riseman, F. G. Stockton, C. Wogrin","doi":"10.1109/ARITH.1975.6156983","DOIUrl":"https://doi.org/10.1109/ARITH.1975.6156983","url":null,"abstract":"Recently, while considering the connection of a 48 bit word computer to a 16 bit computer, we felt the need for a fast and inexpensive device that would multiply a binary address by a factor of three. Since 3N = N + 2N, there is an obvious solution of providing a normal adder circuit and presenting one set of inputs with N and the other with N-shifted left one place. But, there is a great deal of redundancy here since knowing one input we have complete knowledge of the other.","PeriodicalId":360742,"journal":{"name":"1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115272848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of an arithmetic element for serial processing in an iterative structure","authors":"L. Goyal","doi":"10.1109/ARITH.1975.6156986","DOIUrl":"https://doi.org/10.1109/ARITH.1975.6156986","url":null,"abstract":"This paper describes the arithmetic and logic design of the digit processing logic of an arithmetic element. The arithmetic element is used in an iterative structure and arithmetic processing takes place serially on a digit by digit basis with the most significant digit first. Starting from the arithmetic specification of the digit processing logic, the arithmetic design (namely, the choice of number system, number representation and the digit algorithm) is developed. Algebraic and logic designs of the logic necessary to execute the digit algorithm and its implication for LSI implementation are discussed.","PeriodicalId":360742,"journal":{"name":"1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115142078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Programmer-controlled roundoff and the selection of a stable roundoff rule","authors":"R. A. Keir","doi":"10.1109/ARITH.1975.6156989","DOIUrl":"https://doi.org/10.1109/ARITH.1975.6156989","url":null,"abstract":"The author suggests that every computer with floating-point addition and subtraction should have PSW control able roundoff facilities. Yohe's catalog should be included. There should also be a stable roundoff mode using the round-to-off or round-to-even rule based on whether the radix is divisible by four or only by two.","PeriodicalId":360742,"journal":{"name":"1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1975-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134639361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}