Analysis and Design of CMOS Clocking Circuits for Low Phase Noise最新文献

DLL loop dynamics and jitter DLL循环动态和抖动

Analysis and Design of CMOS Clocking Circuits for Low Phase Noise Pub Date : 2020-07-01 DOI: 10.1049/pbcs059e_ch7

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PLL loop dynamics and jitter 锁相环动力学和抖动

Analysis and Design of CMOS Clocking Circuits for Low Phase Noise Pub Date : 2020-07-01 DOI: 10.1049/pbcs059e_ch6

W. Bae, D. Jeong

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CMOS oscillators CMOS振荡器

Analysis and Design of CMOS Clocking Circuits for Low Phase Noise Pub Date : 2020-07-01 DOI: 10.1049/pbcs059e_ch3

{"title":"CMOS oscillators","authors":"","doi":"10.1049/pbcs059e_ch3","DOIUrl":"https://doi.org/10.1049/pbcs059e_ch3","url":null,"abstract":"INTRODUCTION This note describes several square wave oscillators that can be built using CMOS logic elements. These circuits offer the following advantages: • Guaranteed startability • Relatively good stability with respect to power supply variations • Operation over a wide supply voltage range (3V to 15V) • Operation over a wide frequency range from less than 1 Hz to about 15 MHz • Low power consumption (see AN-90) • Easy interface to other logic families and elements including TTL Several RC oscillators and two crystal controlled oscillators are described. The stability of the RC oscillator will be sufficient for the bulk of applications; however, some applications will probably require the stability of a crystal. Some applications that require a lot of stability are: 1. Timekeeping over a long interval. A good deal of stability is required to duplicate the performance of an ordinary wrist watch (about 12 ppm). This is, of course, obtainable with a crystal. However, if the time interval is short and/or the resolution of the timekeeping device is relatively large, an RC oscillator may be adequate. For example: if a stopwatch is built with a resolution of tenths of seconds and the longest interval of interest is two minutes, then an accuracy of 1 part in 1200 (2 minutes x 60 seconds/minute x 10 tenth/second) may be acceptable since any error is less than the resolution of the device. 2. When logic elements are operated near their specified limits. It may be necessary to maintain clock frequency accuracy within very tight limits in order to avoid exceeding the limits of the logic family being used, or in which the timing relationships of clock signals in dynamic MOS memory or shift register systems must be preserved. 3. Baud rate generators for communications equipment. 4. Any system that must interface with other tightly specified systems. Particularly those that use a “handshake” technique in which Request or Acknowledge pulses must be of specific widths.","PeriodicalId":357134,"journal":{"name":"Analysis and Design of CMOS Clocking Circuits for Low Phase Noise","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124076487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Survey on state-of-the-art clock generators 最新时钟发生器的调查

Analysis and Design of CMOS Clocking Circuits for Low Phase Noise Pub Date : 2020-07-01 DOI: 10.1049/pbcs059e_appendixb

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Introduction to phase noise and jitter 介绍相位噪声和抖动

Analysis and Design of CMOS Clocking Circuits for Low Phase Noise Pub Date : 2020-07-01 DOI: 10.1049/pbcs059e_ch2

W. Bae, D. Jeong

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Back Matter 回到问题

Analysis and Design of CMOS Clocking Circuits for Low Phase Noise Pub Date : 2020-07-01 DOI: 10.1049/pbcs059e_bm

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Phase noise suppression techniques 2: all-digital PLL 相位噪声抑制技术2:全数字锁相环

Analysis and Design of CMOS Clocking Circuits for Low Phase Noise Pub Date : 2020-07-01 DOI: 10.1049/pbcs059e_ch9

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Phase noise suppression techniques 1: subsampling PLL 相位噪声抑制技术1:分采样锁相环

Analysis and Design of CMOS Clocking Circuits for Low Phase Noise Pub Date : 2020-07-01 DOI: 10.1049/pbcs059e_ch8

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Phase noise suppression techniques 3: injection locking 相位噪声抑制技术3:注入锁定

Analysis and Design of CMOS Clocking Circuits for Low Phase Noise Pub Date : 2020-07-01 DOI: 10.1049/pbcs059e_ch10

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