PLL loop dynamics and jitter

In this chapter, the phase domain transfer function of each building block of the PLL is described. Because the intent of the PLL is "phase lock," the analysis should be done in the phase domain, so it is assumed that a phase error (O m ) is applied to the input of the PLL. For the derivation of the loop dynamics, Oerr is assumed to be small enough and to be introduced after the PLL achieves the phase lock.