相位噪声抑制技术2:全数字锁相环

{"title":"相位噪声抑制技术2:全数字锁相环","authors":"","doi":"10.1049/pbcs059e_ch9","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":357134,"journal":{"name":"Analysis and Design of CMOS Clocking Circuits for Low Phase Noise","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Phase noise suppression techniques 2: all-digital PLL\",\"authors\":\"\",\"doi\":\"10.1049/pbcs059e_ch9\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"\",\"PeriodicalId\":357134,\"journal\":{\"name\":\"Analysis and Design of CMOS Clocking Circuits for Low Phase Noise\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Analysis and Design of CMOS Clocking Circuits for Low Phase Noise\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1049/pbcs059e_ch9\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analysis and Design of CMOS Clocking Circuits for Low Phase Noise","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/pbcs059e_ch9","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}