2006 27th IEEE International Real-Time Systems Symposium (RTSS'06)最新文献

筛选

英文中文

A Cognac-Glass Algorithm for Conditionally Guaranteed Budgets 条件保证预算的Cognac-Glass算法

2006 27th IEEE International Real-Time Systems Symposium (RTSS'06) Pub Date : 2006-12-05 DOI: 10.1109/RTSS.2006.5

R. J. Bril, W. Verhaegh, C. C. Wüst

{"title":"A Cognac-Glass Algorithm for Conditionally Guaranteed Budgets","authors":"R. J. Bril, W. Verhaegh, C. C. Wüst","doi":"10.1109/RTSS.2006.5","DOIUrl":"https://doi.org/10.1109/RTSS.2006.5","url":null,"abstract":"To analyse the schedulability of conditionally guaranteed budgets (CGBs) in the context of fixed-priority preemptive scheduling (FPPS), we present a so-called cognac-glass algorithm (CGA). CGBs have been conceived in the context of software video processing for consumer terminals to exploit the relative importance of applications. CGBs are similar to normal budgets, but are only conditionally guaranteed. This paper presents the schedulability analysis of CGBs under FPPS, based on both best-case and worst-case analysis techniques. We show that because both techniques are used, it is not straightforward to base the analysis on a critical instant. We therefore have to investigate multiple phasings of budgets during the analysis, for which we present a so-called cognac-glass algorithm. We derive that it suffices to consider only a subset of so-called dominating values for the phasing, which improves the efficiency of our algorithm. Given our analysis, we evaluate the effectiveness of CGBs, and conclude that CGBs are particularly useful for software video processing. Finally, we briefly compare our approach for CGBs with existing analysis techniques for hierarchical FPPS, and illustrate that best-case analysis techniques and a CGA can reduce the inherent pessimism in these existing techniques","PeriodicalId":353932,"journal":{"name":"2006 27th IEEE International Real-Time Systems Symposium (RTSS'06)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122809139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

MCGREP--A Predictable Architecture for Embedded Real-Time Systems MCGREP——嵌入式实时系统的可预测架构

2006 27th IEEE International Real-Time Systems Symposium (RTSS'06) Pub Date : 2006-12-05 DOI: 10.1109/RTSS.2006.28

J. Whitham, N. Audsley

{"title":"MCGREP--A Predictable Architecture for Embedded Real-Time Systems","authors":"J. Whitham, N. Audsley","doi":"10.1109/RTSS.2006.28","DOIUrl":"https://doi.org/10.1109/RTSS.2006.28","url":null,"abstract":"Real-time systems design involves many important choices, including that of the processor. The fastest processors achieve performance by utilizing architectural features that make them unpredictable, leading to difficulties proving offline that application process deadlines will be met, in the worst-case. Utilizing slower, more predictable processors, may not provide sufficient instruction throughput to execute all required application processes. This exposes a key trade-off in processor selection for real-time systems: predictability versus instruction throughput. This paper proposes MCGREP, a novel CPU architecture that combines predictability, high instruction throughput and flexibility. MCGREP is entirely microprogrammed, with multiple execution units. Basic operation involves implementation of a conventional set of CPU instructions in microcode - MCGREP then executes object code suitably compiled. Advanced operation allows the application to dynamically load new microcode, enabling new application specific instructions to increase overall performance. MCGREP is implemented upon reconfigurable logic (FPGA) - an increasingly important platform for the embedded RTS. Custom microcode configurations for new instructions are generated from C source. MCGREP is shown to have performance comparable to two popular FPGA softcore CPUs (OpenRISC and Microblaze, the latter a commercial product). Flexibility is demonstrated by implementing an existing instruction set (OpenRISC) in microcode, with application-specific instructions to improve overall performance. As a further demonstration, predictable two-level interrupt and synchronization mechanisms are programmed in microcode","PeriodicalId":353932,"journal":{"name":"2006 27th IEEE International Real-Time Systems Symposium (RTSS'06)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116865163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Faster Verification of RTL-Specified Systems via Decomposition and Constraint Extension 基于分解和约束扩展的rtl指定系统的快速验证

2006 27th IEEE International Real-Time Systems Symposium (RTSS'06) Pub Date : 2006-12-05 DOI: 10.1109/RTSS.2006.23

S. Andrei, A. Cheng

{"title":"Faster Verification of RTL-Specified Systems via Decomposition and Constraint Extension","authors":"S. Andrei, A. Cheng","doi":"10.1109/RTSS.2006.23","DOIUrl":"https://doi.org/10.1109/RTSS.2006.23","url":null,"abstract":"Embedded and real-time systems are increasingly common and complex, requiring formal specification and verification in order to guarantee their satisfaction of desirable safety and timing requirements. Real-time logic (RTL) has been used to capture both the specification of a real-time system and the desirable safety assertions with respect to this system specification. A verification procedure then determines whether the safety assertions hold with respect to the system specification. However, the satisfiability problem for RTL, as well as for other first-order logics, is undecidable. Consequently, efforts have been focused on identifying non-trivial classes of formulas sufficiently practical for describing industrial real-time systems for which the verification and debugging can be done via efficient heuristics. One such class of formulas is the so-called path RTL. The first contribution of this paper is to extend the existing path RTL class without sacrificing the time complexity of the traditional path RTL heuristic for verification. This implies that we can specify and verify real-time systems, which we were unable to do using the existing path RTL, in the extended path RTL. For real-time systems with large specifications, there is a lot of room for improvement in the algorithms used for verification and debugging. The second contribution of this paper is an efficient method to perform verification and debugging of real-time systems specifications using decomposition techniques. Our idea is to decompose the constraint graph, used in existing approaches, into independent subgraphs so that it is no longer necessary to analyze the entire specification at once, but rather its individual and smaller components. We have implemented this method in the Java-based DEVA-RTL tool and tested it on several industrial real-time systems","PeriodicalId":353932,"journal":{"name":"2006 27th IEEE International Real-Time Systems Symposium (RTSS'06)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124963758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

首页上一页