2021 IEEE 34th International System-on-Chip Conference (SOCC)最新文献

Track A - Virtual Room 1 - Session Chair: Lan-Da Van0 专场A -虚拟房间1 -会议主持人:范兰达

2021 IEEE 34th International System-on-Chip Conference (SOCC) Pub Date : 2021-09-14 DOI: 10.1109/SOCC52499.2021.9739246

引用次数: 0

Dual-Band GSM Energy Harvester for a Duty-Cycle Approach in 180nm CMOS Technology 180nm CMOS技术的占空比双波段GSM能量采集器

2021 IEEE 34th International System-on-Chip Conference (SOCC) Pub Date : 2021-09-14 DOI: 10.1109/SOCC52499.2021.9739239

H. Hernández, D. A. Pontes, B. Soares, D. Carvalho, W. Noije

引用次数: 1

Real-Time FPGA-Based Binocular Stereo Vision System with Semi-Global Matching Algorithm 基于半全局匹配算法的实时fpga双目立体视觉系统

2021 IEEE 34th International System-on-Chip Conference (SOCC) Pub Date : 2021-09-14 DOI: 10.1109/SOCC52499.2021.9739626

Zhuoyu Chen, Pingcheng Dong, Zhuoao Li, Ruoheng Yao, Yunhao Ma, Xiwei Fang, Huanshihong Deng, Wenyue Zhang, Lei Chen, F. An

{"title":"Real-Time FPGA-Based Binocular Stereo Vision System with Semi-Global Matching Algorithm","authors":"Zhuoyu Chen, Pingcheng Dong, Zhuoao Li, Ruoheng Yao, Yunhao Ma, Xiwei Fang, Huanshihong Deng, Wenyue Zhang, Lei Chen, F. An","doi":"10.1109/SOCC52499.2021.9739626","DOIUrl":"https://doi.org/10.1109/SOCC52499.2021.9739626","url":null,"abstract":"Binocular stereo vision, which is an attractive topic in the computer vision area, mainly focuses on extracting depth information through a stereo matching algorithm. The semi-global matching algorithm (SGM) is well-studied but is hard to be applied in real-time because of the high computational cost. In this work, we report an FPGA-based stereo vision system for the SGM. The system contains a camera controller, a module for image rectification, and the SGM accelerator. The SGM accelerator module can extract the depth information with very high speed by a parallel pixel-level pipeline architecture. The left-right check module further ensures the quality of the disparity map. We implement the system on the Stratix-V platform with a 14.9% error rate and it consumes about 58K LUTs, 59K registers, and 5.2M bits of on-chip memory. The maximum working frequency can reach up to 135.96 MHz for the XGA (1024×768) video and 128 disparity range with the power dissipation of 4.302 W and the processing speed of 173 XGA-frames per second.","PeriodicalId":352995,"journal":{"name":"2021 IEEE 34th International System-on-Chip Conference (SOCC)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133145348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Power Swapper: Approximate Functional Block Assisted Cryptosystem Security 电源交换器:近似功能块辅助密码系统安全

2021 IEEE 34th International System-on-Chip Conference (SOCC) Pub Date : 2021-09-14 DOI: 10.1109/SOCC52499.2021.9739304

Abhijitt Dhavlle, S. Rafatirad, H. Homayoun, Sai Manoj Pudukotai Dinakarrao

{"title":"Power Swapper: Approximate Functional Block Assisted Cryptosystem Security","authors":"Abhijitt Dhavlle, S. Rafatirad, H. Homayoun, Sai Manoj Pudukotai Dinakarrao","doi":"10.1109/SOCC52499.2021.9739304","DOIUrl":"https://doi.org/10.1109/SOCC52499.2021.9739304","url":null,"abstract":"The hardware security domain in the recent years has experienced a plethora of threats of which side-channel attacks (SCAs) has been one of the emerging threats. These SCAs function by exploiting the side-channels which invariably leak important data during an application’s execution. The information leaked through side-channels are inherent characteristics of the system and is often unintentional. This information can be microarchitectural or physical information such as power consumption, thermal maps, timing of the operation, acoustics, and cache-trace. Intercepting secret information based on the study of power signature is a subdivision of SCAs where power consumption information serves as a covert channel leaking crucial information about the executed operations. Such physical SCAs are known to be a significant threat to cryptosystems such as AES (Advances Encryption Standard) and can reveal the encryption key efficiently. To overcome such concerns and protect the data integrity, we introduce Power Swapper in this work. The proposed Power Swapper thwarts the attack by randomly choosing one of the multiple modules that perform the intended activity, but have power consumption different than a standard implementation and can lead to similar power consumption as one of the other modules that perform a different operation. To achieve this, we introduce carefully crafted swapping of the standby modules that are responsible for the AES operation thus deluding the attacker without hurting the crypto operations. To minimize the overheads, we design reconfigurable computing elements that can perform a given operation, but with different power consumption depending on the configuration. This methodology has been validated for the AES power analysis attack and the key information observed by the attacker is seen to be completely futile, indicating the success of the proposed method.","PeriodicalId":352995,"journal":{"name":"2021 IEEE 34th International System-on-Chip Conference (SOCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126581603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

SOCC 2021 Cover Page SOCC 2021封面

2021 IEEE 34th International System-on-Chip Conference (SOCC) Pub Date : 2021-09-14 DOI: 10.1109/socc52499.2021.9739230

引用次数: 0

SOCC 2021 Steering Committee SOCC 2021指导委员会

2021 IEEE 34th International System-on-Chip Conference (SOCC) Pub Date : 2021-09-14 DOI: 10.1109/socc52499.2021.9739249

引用次数: 0

A Two-Stage Path Planning Engine for Robot Navigation System 机器人导航系统的两阶段路径规划引擎

2021 IEEE 34th International System-on-Chip Conference (SOCC) Pub Date : 2021-09-14 DOI: 10.1109/SOCC52499.2021.9739379

Yu-En Hsu, Yen-Chin Liao, Hsie-Chia Chang

{"title":"A Two-Stage Path Planning Engine for Robot Navigation System","authors":"Yu-En Hsu, Yen-Chin Liao, Hsie-Chia Chang","doi":"10.1109/SOCC52499.2021.9739379","DOIUrl":"https://doi.org/10.1109/SOCC52499.2021.9739379","url":null,"abstract":"This paper presents a two-stage path planning architecture, realized by using a general-purpose CPU as a global planner and a proposed path planning engine as a local planner, solving a path planning problem hierarchically. By the use of heterogeneity, the hardware-software cooperation architecture can take advantages of both hardware and software approach and achieve both generalization and hardware-acceleration. The proposed path planning engine is based on A* algorithm, several hardware-friendly optimization techniques are applied or proposed to reduce the time complexity of searching. The coefficient modification avoids the usage of square root hardware. Then, the priority list reordering fully utilizes the memory bandwidth. Finally, we optimized the critical path and achieved 333MHz operating frequency.The proposed system is established and verified in Xilinx PYNQ-Z2 platform using ARM A9 processor as global planner and FPGA as local planner. Moreover, the proposed path planning engine is implemented in TSMC 40nm CMOS process and integrated 296.1k logic gates in 0.28mm2 chip area. It achieves 9.6µs/task latency and 0.16µJ/task energy consumption in 2D and 27.6µs/task latency and 0.48µJ/task energy consumption in 3D.","PeriodicalId":352995,"journal":{"name":"2021 IEEE 34th International System-on-Chip Conference (SOCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131681635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Keynote Speaker: Kaushik Roy 主讲人:Kaushik Roy

2021 IEEE 34th International System-on-Chip Conference (SOCC) Pub Date : 2021-09-14 DOI: 10.1109/SOCC52499.2021.9739529

引用次数: 0

NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators 神经形态加速器集成的系统级虚拟平台

2021 IEEE 34th International System-on-Chip Conference (SOCC) Pub Date : 2021-09-14 DOI: 10.1109/SOCC52499.2021.9739585

M. Galicia, Ali BanaGozar, Karl J. X. Sturm, Felix Staudigl, S. Stuijk, H. Corporaal, R. Leupers

{"title":"NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators","authors":"M. Galicia, Ali BanaGozar, Karl J. X. Sturm, Felix Staudigl, S. Stuijk, H. Corporaal, R. Leupers","doi":"10.1109/SOCC52499.2021.9739585","DOIUrl":"https://doi.org/10.1109/SOCC52499.2021.9739585","url":null,"abstract":"Executing neural network (NN) applications on general-purpose processors result in a large power and performance overhead, due to the high cost of data movement between the processor and the main memory. Neuromorphic computing systems based on memristor crossbars, perform the NN main operation i.e., vector-matrix multiplications (VMM) in an efficient way in the analog domain. Thus, they circumvent the costly energy overhead of its digital counterpart. It can be expected that neuromorphic systems will be used initially as complements to current high-performance systems rather than as a replacement. This paper presents NeuroVP, a virtual platform integrating a neuromorphic accelerator, developed in SystemC that can model functionality, timing, and power consumption of the components integrating the system. Using NeuroVP to evaluate performance and power consumption at the electronic system level (ESL), it is corroborated that the execution of NN applications with a neuromorphic accelerator yields of up to 46x higher power efficiency and 26x speedup relative to a general-purpose computing system.","PeriodicalId":352995,"journal":{"name":"2021 IEEE 34th International System-on-Chip Conference (SOCC)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131773293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks 量化神经网络的分层可重构过程元设计

2021 IEEE 34th International System-on-Chip Conference (SOCC) Pub Date : 2021-09-14 DOI: 10.1109/SOCC52499.2021.9739487

Yu-Guang Chen, Chin-Wei Hsu, H. Chiang, Tsung-Han Hsieh, Jing-Yang Jou

{"title":"A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks","authors":"Yu-Guang Chen, Chin-Wei Hsu, H. Chiang, Tsung-Han Hsieh, Jing-Yang Jou","doi":"10.1109/SOCC52499.2021.9739487","DOIUrl":"https://doi.org/10.1109/SOCC52499.2021.9739487","url":null,"abstract":"Convolution neural networks are very popular for various applications. However, data size and accuracy are the two major concerns to perform efficient and effective computations. In conventional CNN models, 32bits data are frequently used to maintain high accuracy. However, performing a bunch of 32bits multiply-and-accumulate (MAC) operations causes significant computing efforts as well as power consumptions. Therefore, recently researchers develop various methods to reduce data size and speed up calculations. Quantization is one of the techniques which reduces the number of the bits of data and the computational complexity at the cost of accuracy loss. To provide better computation effort and accuracy trade-off, different bitwidth may be applied to different layers within a CNN model. Therefore, a flexible Processing Element (PE) which can support operations of different bitwidth is in demand. In this paper, we propose a hierarchal PE structure that can support 8bits x 8bits, 8bits x 4bits, 4bits x 4bits and 2bits x 2bits operations. The structure applies the concept of reconfiguration and can avoid the redundant hardware for reconfiguration. Moreover, the concept of pipelining is also adopted in our design to provide better efficiency. The experimental results show that in 2bits x 2bits PE, we can achieve area reduction by 57% and 68% compared to a Precision-Scalable accelerator and Bit Fusion, respectively.","PeriodicalId":352995,"journal":{"name":"2021 IEEE 34th International System-on-Chip Conference (SOCC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132145836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0