Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion最新文献_第2页

An efficient hardware design for cerebellar models using approximate circuits: special session paper 使用近似电路的小脑模型的有效硬件设计:专题会议论文

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion Pub Date : 2017-10-15 DOI: 10.1145/3125502.3125537

Honglan Jiang, Leibo Liu, Jie Han

引用次数: 2

A fast online sequential learning accelerator for IoT network intrusion detection: work-in-progress

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion Pub Date : 2017-10-15 DOI: 10.1145/3125502.3125532

Hantao Huang, Suleman Khalid Rai, Wenye Liu, Hao Yu

引用次数: 3

Heterogeneous redundancy to address performance and cost in multi-core SIMT: work-in-progress 异构冗余以解决多核SIMT中的性能和成本问题:正在进行的工作

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion Pub Date : 2017-10-15 DOI: 10.1145/3125502.3125547

M. Naghashi, S. H. Mozafari, S. Hessabi

引用次数: 0

DOVE: pinpointing firmware security vulnerabilities via symbolic control flow assertion mining (work-in-progress) DOVE:通过符号控制流断言挖掘来精确定位固件安全漏洞(正在进行中)

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion Pub Date : 2017-10-15 DOI: 10.1145/3125502.3125541

Alessandro Danese, G. Pravadelli, V. Bertacco

引用次数: 3

IR-level annotation strategy dealing with aggressive loop optimizations for performance estimation in native simulation: work-in-progress 处理原生模拟中用于性能估计的主动循环优化的ir级注释策略:正在进行中

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion Pub Date : 2017-10-15 DOI: 10.1145/3125502.3125550

Omayma Matoussi, F. Pétrot

{"title":"IR-level annotation strategy dealing with aggressive loop optimizations for performance estimation in native simulation: work-in-progress","authors":"Omayma Matoussi, F. Pétrot","doi":"10.1145/3125502.3125550","DOIUrl":"https://doi.org/10.1145/3125502.3125550","url":null,"abstract":"Originally developed for purely functional verification of software, native or host compiled simulation [6] has gained momentum, thanks to its considerable speedup compared to instruction set simulation (ISS). To obtain a performance model of the software, non-functional information is computed from the target binary code using low-level analysis and back-annotated into the high-level code used to generate it. This annotated functional model is then natively compiled and executed on the host machine for fast software timing [8] estimations. Back-annotating at the right place needs a mapping between the binary instructions and the high-level code statements. So, it is necessary to decide at which stage of the software compilation process the information is back-annotated. There are three possibilities: in the original source code ([7]), in the host binary code ([3]), or in the compiler intermediate representation (IR) ([8], [2]). As compilers perform many optimizations to enhance software performance, the source code and the binary code structures may be radically different. In this work, we define a mapping approach between the compiler's IR and the binary control flow graph (CFG) when a high-level of compiler optimizations (eg. O3 in gcc) is used. Our approach handles aggressive compiler optimizations such as loop unrolling without having to introduce any modification to the compiler.","PeriodicalId":350509,"journal":{"name":"Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127298869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Hampering fault attacks against lattice-based signature schemes: countermeasures and their efficiency (special session) 阻止格签名方案的故障攻击:对策及有效性(专题会议)

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion Pub Date : 2017-10-15 DOI: 10.1145/3125502.3125546

Nina Bindel, Juliane Krämer, Johannes Schreiber

引用次数: 5

Trends, challenges and needs for lattice-based cryptography implementations: special session 基于格的加密实现的趋势、挑战和需求:专题会议

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion Pub Date : 2017-10-15 DOI: 10.1145/3125502.3125559

Hamid Nejatollahi, N. Dutt, Rosario Cammarota

{"title":"Trends, challenges and needs for lattice-based cryptography implementations: special session","authors":"Hamid Nejatollahi, N. Dutt, Rosario Cammarota","doi":"10.1145/3125502.3125559","DOIUrl":"https://doi.org/10.1145/3125502.3125559","url":null,"abstract":"Advances in computing steadily erode computer security at its foundation, calling for fundamental innovations to strengthen the weakening cryptographic primitives and security protocols. At the same time, the emergence of new computing paradigms, such as Cloud Computing and Internet of Everything, demand that innovations in security extend beyond their foundational aspects, to the actual design and deployment of these primitives and protocols while satisfying emerging design constraints such as latency, compactness, energy efficiency, and agility. While many alternatives have been proposed for symmetric key cryptography and related protocols (e.g., lightweight ciphers and authenticated encryption), the alternatives for public key cryptography are limited to post-quantum cryptography primitives and their protocols. In particular, lattice-based cryptography is a promising candidate, both in terms of foundational properties, as well as its application to traditional security problems such as key exchange, digital signature, and encryption/decryption. We summarize trends in lattice-based cryptographic schemes, some fundamental recent proposals for the use of lattices in computer security, challenges for their implementation in software and hardware, and emerging needs.","PeriodicalId":350509,"journal":{"name":"Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126500756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Exploring fast and slow memories in HMP core types: work-in-progress 探索HMP核心类型中的快存储器和慢存储器:正在进行中

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion Pub Date : 2017-10-15 DOI: 10.1145/3125502.3125545

Bryan Donyanavard, Amir Mahdi Hosseini Monazzah, T. Mück, N. Dutt

引用次数: 1

A power-efficient and high performance FPGA accelerator for convolutional neural networks: work-in-progress 一种用于卷积神经网络的高效节能FPGA加速器:正在研究中

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion Pub Date : 2017-10-15 DOI: 10.1145/3125502.3125534

Lei Gong, Chao Wang, Xi Li, Hua-ping Chen, Xuehai Zhou

{"title":"A power-efficient and high performance FPGA accelerator for convolutional neural networks: work-in-progress","authors":"Lei Gong, Chao Wang, Xi Li, Hua-ping Chen, Xuehai Zhou","doi":"10.1145/3125502.3125534","DOIUrl":"https://doi.org/10.1145/3125502.3125534","url":null,"abstract":"Recently, FPGAs have been widely used in the implementation of hardware accelerators for Convolutional Neural Networks (CNN), especially on mobile and embedded devices. However, most of these existing accelerators are designed with the same concept as their ASIC counterparts, that is all operations from different CNN layers are mapped to the same hardware units and work in a multiplexed way. Although this approach improves the generality of these accelerators, it does not take full advantage of reconfigurability and customizability of FPGAs, resulting in a certain degree of computational efficiency degradation, which is even worse on the embedded platforms. In this paper, we propose an FPGA-based CNN accelerator with all the layers mapped to their own on-chip units, and working concurrently as a pipeline. A strategy which can find the optimized paralleling scheme for each layer is proposed to eliminate the pipeline stall and achieve high resource utilization. In addition, a balanced pruning-based method is applied on fully connected (FC) layers to reduce the computational redundancy. As a case study, we implement a widely used CNNs model, LeNet-5, on an embedded FPGA device, Xilinx Zedboard. It can achieve a peak performance of 39.78 GOP/s and the power efficiency with a value 19.6 GOP/s/W which outperforms previous approaches.","PeriodicalId":350509,"journal":{"name":"Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129687492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Data analytics enables energy-efficiency and robustness: from mobile to manycores, datacenters, and networks (special session paper) 数据分析使能源效率和健壮性:从移动到多核、数据中心和网络(特别会议论文)

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion Pub Date : 2017-10-15 DOI: 10.1145/3125502.3125560

S. Pasricha, J. Doppa, K. Chakrabarty, Saideep Tiku, D. Dauwe, Shi Jin, P. Pande

{"title":"Data analytics enables energy-efficiency and robustness: from mobile to manycores, datacenters, and networks (special session paper)","authors":"S. Pasricha, J. Doppa, K. Chakrabarty, Saideep Tiku, D. Dauwe, Shi Jin, P. Pande","doi":"10.1145/3125502.3125560","DOIUrl":"https://doi.org/10.1145/3125502.3125560","url":null,"abstract":"The amount of data generated and collected across computing platforms every day is not only enormous, but growing at an exponential rate. Advanced data analytics and machine-learning techniques have become increasingly essential to analyze and extract meaning from such \"Big Data\". These techniques can be very useful to detect patterns and trends to improve the operational behavior of computing platforms, but they also introduce a number of outstanding challenges: (1) How can we design and deploy data analytics and learning mechanisms to improve energy-efficiency in IoT and mobile devices, without introducing significant software overheads? (2) How to use machine learning and analytics techniques for effective designspace exploration during manycore chip design? (3) How can data analytics and learning improve the reliability and energy-efficiency of large-scale cloud datacenters, to cost-effectively support connected embedded and IoT platforms? (4) How can data analytics detect anomalies and increase robustness in the network backbone of emerging cloud datacenter networks? In this paper, we discuss these outstanding problems and describe far-reaching solutions applicable across the interconnected ecosystem of IoT and mobile devices, manycore chips, datacenters, and networks.","PeriodicalId":350509,"journal":{"name":"Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion","volume":"938 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123064263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2