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A Compact Low-Power SiGe:C BiCMOS Amplifier for 77-81 GHz Automotive Radar 用于77-81 GHz汽车雷达的紧凑型低功耗sigc BiCMOS放大器
2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Pub Date : 2008-02-01 DOI: 10.1109/SMIC.2008.55
B. Schleicher, S. Chartier, G. Fischer, F. Korndorfer, J. Borngraber, T. Feger, H. Schumacher
{"title":"A Compact Low-Power SiGe:C BiCMOS Amplifier for 77-81 GHz Automotive Radar","authors":"B. Schleicher, S. Chartier, G. Fischer, F. Korndorfer, J. Borngraber, T. Feger, H. Schumacher","doi":"10.1109/SMIC.2008.55","DOIUrl":"https://doi.org/10.1109/SMIC.2008.55","url":null,"abstract":"In this paper a single-ended fully integrated Si/SiGe HBT amplifier working at a center frequency of 79 GHz is presented. The amplifier consists of three cascode stages. A trimmable line technique and an efficient DC filtering network were used. The amplifier shows a maximum measured gain of 13.2 dB at exactly 79 GHz and an excellent reverse isolation of more than 40 dB over the whole measured frequency range. Its performance was measured at different temperatures, showing a decrease of 5.3 dB in gain between room temperature and 85degC. The measured -1 dB input compression point is at -15 dBm. The power consumption is 52 mW at a supply voltage of 2.7 V. The circuit has a compact layout and consumes an area of 525 times 500 mum2 including bonding pads.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116086030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Influence of Substrate Parasitic Effects on Power Gain Relation Between CE and CB SiGe HBTs 衬底寄生效应对CE和CB SiGe HBTs功率增益关系的影响
2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Pub Date : 2008-02-01 DOI: 10.1109/SMIC.2008.22
Hai Huang, Z. Ma, P. Ma, M. Rananelli
{"title":"Influence of Substrate Parasitic Effects on Power Gain Relation Between CE and CB SiGe HBTs","authors":"Hai Huang, Z. Ma, P. Ma, M. Rananelli","doi":"10.1109/SMIC.2008.22","DOIUrl":"https://doi.org/10.1109/SMIC.2008.22","url":null,"abstract":"The impact of substrate parasitic effects on the power gain relation between the CE and CB configurations of low-power SiGe HBTs has been analyzed. In comparison to large-area power SiGe HBTs, the speed and small-signal power gain of the device are much higher. Nevertheless, the relative parasitic effects on these small devices are much stronger than that on the large ones. It is found that due to the influence of substrate parasitic effects (input and output coupling between input and output pads), the power gain of CB SiGe HBTs can be dramatically degraded, while the power gain of CE SiGe HBTs is not affected much. The consequence of the different influences of parasitic effects on CE and CB SiGe HBTs is that the intrinsic higher power gain of the CB SiGe HBT than the CE device is lost, which is verified by measurements. Based on the detailed analysis of the substrate parasitic effects, an approach to restoring the superior power gain characteristics of CB SiGe HBTs is proposed.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123615377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Methodology for Design and Modeling of Optimum Quality Spiral Inductors 一种最优质量螺旋电感的设计与建模方法
2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Pub Date : 2008-02-01 DOI: 10.1109/SMIC.2008.32
M. Ballicchia, S. Orcioni
{"title":"A Methodology for Design and Modeling of Optimum Quality Spiral Inductors","authors":"M. Ballicchia, S. Orcioni","doi":"10.1109/SMIC.2008.32","DOIUrl":"https://doi.org/10.1109/SMIC.2008.32","url":null,"abstract":"This paper presents a methodology, based on the regularization theory, to find, in the whole geometric parameter space, the planar spiral inductors with optimum quality factor. A new technique, based on Debye fitting approximation, has been applied to extract a passive equivalent circuit model of these inductors. This model provides an accurate wideband frequency characterization up to 16 GHz.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124084162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Practical Considerations In The Use of CMOS Active Inductors CMOS有源电感使用中的实际考虑
2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Pub Date : 2008-02-01 DOI: 10.1109/SMIC.2008.29
William L. Bucossi, James P. Becker
{"title":"Practical Considerations In The Use of CMOS Active Inductors","authors":"William L. Bucossi, James P. Becker","doi":"10.1109/SMIC.2008.29","DOIUrl":"https://doi.org/10.1109/SMIC.2008.29","url":null,"abstract":"The lack of high quality factor integrated inductors is one of the most significant impediments to realizing high performance radio frequency integrated circuits (RFICs) within conventional digital CMOS. As an alternative to lossy passive spiral inductors, several active inductor topologies have been reported elsewhere which promise higher quality factors and small size. Using transistor level simulation, this paper considers two fundamental active inductor topologies with particular focus on their robustness with regard to variation with process, voltage and temperature. Simulation results reveal that these active inductors suffer significant variation in both realized inductance value and quality factor particularly as a function of transistor variability. The effects of this variability in active inductor performance are highlighted through simulation of their use in a lumped element Wilkinson power divider realized with active inductors.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127686643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Process-Tolerant Ultralow Voltage Digital Subthreshold Design 工艺容错超低电压数字亚阈值设计
2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Pub Date : 2008-02-01 DOI: 10.1109/SMIC.2008.17
K. Roy, J. Kulkarni, Myeong-Eun Hwang
{"title":"Process-Tolerant Ultralow Voltage Digital Subthreshold Design","authors":"K. Roy, J. Kulkarni, Myeong-Eun Hwang","doi":"10.1109/SMIC.2008.17","DOIUrl":"https://doi.org/10.1109/SMIC.2008.17","url":null,"abstract":"We propose process variation tolerant circuit techniques for robust digital subthreshold design. We present an 8times8 process-tolerant FIR filter, working in both super-threshold and subthreshold regions featuring adaptive beta-ratio modulation and integrated level converters. Ultra-dynamic voltage scaling (UVDS) enables the filter operation at 85 mV consuming 40 nW. For memory applications, we propose Schmitt trigger based SRAM bitcell exhibiting built-in process variation tolerance. Functional SRAM with the proposed memory bitcell is demonstrated at 160 mV in 0.13 mum CMOS technology.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130734309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
On the Design of High Performance RF Integrated Inductors on High Resistively Thin Film 65 nm SOI CMOS Technology 基于高阻性薄膜65纳米SOI CMOS技术的高性能射频集成电感器设计
2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Pub Date : 2008-02-01 DOI: 10.1109/SMIC.2008.31
F. Gianesello, D. Gloria, C. Raynaud, S. Montusclat, S. Boret, P. Touret
{"title":"On the Design of High Performance RF Integrated Inductors on High Resistively Thin Film 65 nm SOI CMOS Technology","authors":"F. Gianesello, D. Gloria, C. Raynaud, S. Montusclat, S. Boret, P. Touret","doi":"10.1109/SMIC.2008.31","DOIUrl":"https://doi.org/10.1109/SMIC.2008.31","url":null,"abstract":"During past years, High Resistivity (HR) SOI CMOS technology has emerged as a promising one for the integration of RF applications, mainly because of the improvement of passive component related to HR substrate. This paper summarizes, for the first time, an in depth analysis of different optimization scheme suitable for on-chip inductors fabricated on HR substrate, using advanced 65 nm SOI CMOS technology with 6 copper metal levels. Measurement results demonstrated that proposed optimized SOI inductor architectures, integrated in a standard advanced digital back-end of line (BEOL), could address high quality factor (single ended quality factor greater than 20), have high current capability (up to 260 mA @ 125degC) or could enable a huge area saving (up to 50 %).","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132909772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Suppression of Digital Noise Coupling on LNA in 0.13-μm RFCMOS Technology by Global Guard Rings 基于全局保护环的0.13 μm RFCMOS技术中LNA数字噪声耦合抑制
2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Pub Date : 2008-02-01 DOI: 10.1109/SMIC.2008.58
Seungyong Lee, Kihan Kim, Taehyoun Oh, I. Song, Hyungcheol Shin, Moon-Ho Kim, J. Rieh
{"title":"Suppression of Digital Noise Coupling on LNA in 0.13-μm RFCMOS Technology by Global Guard Rings","authors":"Seungyong Lee, Kihan Kim, Taehyoun Oh, I. Song, Hyungcheol Shin, Moon-Ho Kim, J. Rieh","doi":"10.1109/SMIC.2008.58","DOIUrl":"https://doi.org/10.1109/SMIC.2008.58","url":null,"abstract":"Digital noise coupling on the noise-sensitive RF and analog circuits through substrate continues to grow as a critical issue as the on-chip integration of digital and RF/analog becomes increasingly popular with the advent of SoC approach. In this work, the effect of digital noise coupling on a 5.8-GHz LNA in 0.13 mum RFCMOS technology was investigated in terms of the noise figure. The noise figure degradation was compared for various magnitudes and clock frequencies of the digital signal applied. Further, the suppression of the noise coupling on the LNA by the global guard ring was demonstrated and compared for various guard ring bias schemes.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121398670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Substrate Noise Rejection in a New Mixed-Signal Integration Technology 一种新型混合信号集成技术中的衬底噪声抑制
2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Pub Date : 2008-02-01 DOI: 10.1109/SMIC.2008.43
H. Sharifi, S. Mohammadi
{"title":"Substrate Noise Rejection in a New Mixed-Signal Integration Technology","authors":"H. Sharifi, S. Mohammadi","doi":"10.1109/SMIC.2008.43","DOIUrl":"https://doi.org/10.1109/SMIC.2008.43","url":null,"abstract":"In this paper, a new mixed-signal substrate noise rejection technique is proposed and implemented using a recently-developed self-aligned wafer-level integration technology (SAWLIT). In this technique, chips with any thickness can be used. Using sidewall metallization of cavities in an interposer substrate, truly grounded Faraday-cage structures are realized. The simulation and measurement results show that a high-resistivity silicon substrate can suppress the substrate noise by more than 60dB for the frequency of less than 1 GHz. For the frequency range of 1GHz to 25GHz, using the grounded Faraday-cage, the isolation can be improved to less than -60dB. For the low-resistivity silicon substrate, the substrate coupling is worse than the high-resistivity Si, however, using sidewall metallization, the isolation can be improved to below -60dB. To our knowledge, these are the best values reported for isolation improvement of thick silicon substrates and chips using a very thin layer of metallization.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115846468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Ultra-Wideband Resistive-Feedback Low-Noise Amplifier with Noise Cancellation in 0.18μm Digital CMOS 基于0.18μm数字CMOS的超宽带电阻反馈降噪放大器
2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Pub Date : 2008-02-01 DOI: 10.1109/SMIC.2008.61
Jianyun Hu, Yunliang Zhu, Hui Wu
{"title":"An Ultra-Wideband Resistive-Feedback Low-Noise Amplifier with Noise Cancellation in 0.18μm Digital CMOS","authors":"Jianyun Hu, Yunliang Zhu, Hui Wu","doi":"10.1109/SMIC.2008.61","DOIUrl":"https://doi.org/10.1109/SMIC.2008.61","url":null,"abstract":"We present a wideband resistive feedback CMOS low-noise amplifier (LNA) with noise cancellation technique for ultra-wideband applications. The LNA achieves a 3-dB bandwidth of 0.7-6.5 GHz, power gain of 12.5 dB, and noise figure of 3.5-4.2 dB within the 3-dB bandwidth. The input matching is better than -11 dB from 0.7 to 12 GHz. The IIP3 is measured -5 dBm at 5 GHz. It is implemented in a 0.18 mum standard digital CMOS technology, occupies an area of 0.78 mmtimes0.68 mm, and consumes 11.1 mW from a 1.8 V supply.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"01 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129672706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Ultra-Miniaturized Integrated Cavities on High-Resistivity Silicon Thin-Film MCM-D Technology 基于高电阻率硅薄膜MCM-D技术的超小型化集成腔
2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Pub Date : 2008-02-01 DOI: 10.1109/SMIC.2008.41
G. Posada, G. Carchon, B. Nauwelaers, W. De Raedt
{"title":"Ultra-Miniaturized Integrated Cavities on High-Resistivity Silicon Thin-Film MCM-D Technology","authors":"G. Posada, G. Carchon, B. Nauwelaers, W. De Raedt","doi":"10.1109/SMIC.2008.41","DOIUrl":"https://doi.org/10.1109/SMIC.2008.41","url":null,"abstract":"Millimeter-wave commercial communication systems are getting a lot of attention in the recent years, and therefore there is a need of implementing miniaturized high-quality passive components at these frequencies. In this paper, we demonstrate the integration of ultra-miniaturized cavities on the thin-film multi-chip module technology (MCM-D) by using through-substrate vias on 100 mum thick high-resistivity silicon (HRSi) wafers. Having HRSi as filling material, the proposed cavities are 3.4 times smaller than air filled cavities. Being integrated cavities, no assembly step is needed, which is an advantage as compared to air filled cavities where wafer stacking is required. The influence of leakage through the via fences is studied in detail showing that having a via diameter of 100 mum, and a pitch of 220 mum, one via row is enough to eliminate radiation at 29 GHz, but at 60 GHz 2 via rows are necessary. Additionally, this study shows that the probe feeding mechanism used in this work is very effective and does not lead to any leakage. Second-order filters using integrated cavities are demonstrated at 29 GHz and 60 GHz yielding low losses and a highly accurate center frequency prediction the first time that the filters were manufactured. Being able to implement small and high-quality components, the proposed technology is a viable platform for the implementation of commercial millimeter-wave components.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129688356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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