Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems最新文献

Supporting user-friendly analysis of timing constraints 支持用户友好的时间约束分析

Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems Pub Date : 1995-11-01 DOI: 10.1145/216636.216668

Lo Ko, D. Whalley, M. Harmon

引用次数: 18

Re-usable software design for programmable logic controllers 可编程逻辑控制器的可重用软件设计

Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems Pub Date : 1995-11-01 DOI: 10.1145/216636.216651

F. Bonfatti, G. Gadda, P. Monari

引用次数: 20

Language constructs and transformation for hard real-time systems 硬实时系统的语言构造与转换

Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems Pub Date : 1995-11-01 DOI: 10.1145/216636.216654

Tai M. Chung, H. Dietz

引用次数: 15

Static timing analysis of real-time systems 实时系统的静态时序分析

Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems Pub Date : 1995-11-01 DOI: 10.1145/216636.216664

Muriel Jourdan, F. Maraninchi

引用次数: 7

Compiler support for software-based cache partitioning 编译器支持基于软件的缓存分区

Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems Pub Date : 1995-11-01 DOI: 10.1145/216636.216677

F. Mueller

{"title":"Compiler support for software-based cache partitioning","authors":"F. Mueller","doi":"10.1145/216636.216677","DOIUrl":"https://doi.org/10.1145/216636.216677","url":null,"abstract":"Cache memories have become an essential part of modern processors to bridge the increasing gap between fast processors and slower main memory. Until recently, cache memories were thought to impose unpredictable execution time behavior for hard real-time systems. But recent results show that the speedup of caches can be exploited without a significant sacrifice of predictability. These results were obtained under the assumption that real-time tasks be scheduled non-preemptively.This paper introduces a method to maintain predictability of execution time within preemptive, cached real-time systems and discusses the impact on compilation support for such a system. Preemptive systems with caches are made predictable via software-based cache partitioning. With this approach, the cache is divided into distinct portions associated with a real-time task, such that a task may only use its portion. The compiler has to support instruction and data partitioning for each task. Instruction partitioning involves non-linear control-flow transformations, while data partitioning involves code transformations of data references. The impact on execution time of these transformations is also discussed.","PeriodicalId":349852,"journal":{"name":"Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130676012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 167

Worst-case execution time analysis on modern processors 现代处理器的最坏情况执行时间分析

Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems Pub Date : 1995-11-01 DOI: 10.1145/216636.216650

K. Nilsen, B. Rygg

引用次数: 51

Software synthesis for real-time information processing systems 实时信息处理系统的软件综合

Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems Pub Date : 1995-11-01 DOI: 10.1145/216636.216658

M. Cornero, F. Thoen, G. Goossens, F. Curatelli

引用次数: 34

Scheduling of hard aperiodic tasks 非周期硬任务调度

Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems Pub Date : 1995-11-01 DOI: 10.1145/216636.216647

Jongwon Lee, Sungyoung Lee, Hyungill Kim

引用次数: 1

Verus: a tool for quantitative analysis of finite-state real-time systems Verus:有限状态实时系统的定量分析工具

Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems Pub Date : 1995-11-01 DOI: 10.1145/216636.216661

S. Campos, E. Clarke, W. Marrero, M. Minea

{"title":"Verus: a tool for quantitative analysis of finite-state real-time systems","authors":"S. Campos, E. Clarke, W. Marrero, M. Minea","doi":"10.1145/216636.216661","DOIUrl":"https://doi.org/10.1145/216636.216661","url":null,"abstract":"Symbolic model checking is a technique for verifying finite-state concurrent systems. Models with up to 1030 states can often be verified in minutes. In this paper, we present a new tool to analyze real-time systems, based on this technique. We have designed a language, called Verus, for the description of real-time systems. Such a description is compiled into a state-transition graph and represented symbolically using binary decision diagrams. We have developed new algorithms for exploring the state space and computing quantitative information about the system. In addition to determining the exact bounds on the length of the time interval between two specified events, we compute the number of occurrences of an event in such an interval. This technique allows us to determine performance measures such as schedulability, response time, and system load. Our algorithms produce more detailed information than traditional methods. This information leads to a better understanding of the behavior of the system, in addition to verifying if its timing requirements are satisfied. We integrate these ideas into the Verus tool, currently under development. To demonstrate how our technique works, we have verified a robotics control system. The results obtained demonstrate that our method can be successfully applied in the analysis of real-time system designs.","PeriodicalId":349852,"journal":{"name":"Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121848041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 60

Automatic generation of scheduling and communication code in real-time parallel programs 在实时并行程序中自动生成调度和通信代码

Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems Pub Date : 1995-11-01 DOI: 10.1145/216636.216679

A. Bakkers, J. Sunter, Evert Ploeg

{"title":"Automatic generation of scheduling and communication code in real-time parallel programs","authors":"A. Bakkers, J. Sunter, Evert Ploeg","doi":"10.1145/216636.216679","DOIUrl":"https://doi.org/10.1145/216636.216679","url":null,"abstract":"Inter-process communication and scheduling are notorious problem areas in the design of real-time systems. Using CASE tools, the system design phase will in general result in a system description in the form of parallel processes. Manual allocation of these processes to processors may result in error prone and/or slow communication code. Scheduling of the processes, necessary to meet timing constraints, is also a tedious task that takes many iterations. The described design tools result in code that is comparable in quality and performance with expert manual realization. Many network layers have been implemented to relieve the user from the low-level programming of communication software. However, the increase in user-friendliness is usually paid with performance degradation. The proposed approach combines user-friendliness with high performance by generating communication software that is tailor-made for the application. A similar approach is followed with the scheduling software. Schedulers in the form of a built-in a kernel are available all the time and cause overhead all the time. The proposed preprocessor tool generates scheduling software after analyzing the timing requirements of the particular application. This results in simple code for simple timing requirements and more complicated code for complex timing requirements. The tools have been implemented in Occam for use on a transputer. However, the results are valid for any distributed memory machine.","PeriodicalId":349852,"journal":{"name":"Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132001014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2