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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)最新文献

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A novel architecture design for multicode CDMA rake receiver 一种新的多码码分多址接收机结构设计
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824126
Sangyun Hwang, Seongjoo Lee, Jae-Seok Kim, Chae K. Lee, Sunghwan Jun
{"title":"A novel architecture design for multicode CDMA rake receiver","authors":"Sangyun Hwang, Seongjoo Lee, Jae-Seok Kim, Chae K. Lee, Sunghwan Jun","doi":"10.1109/APASIC.1999.824126","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824126","url":null,"abstract":"We propose a new architecture design for the Multicode CDMA (MC-CDMA) rake receiver. It contains one searcher module, three independent fat finger modules, and one combiner for the demodulation of high-rate data. We compare the hardware complexity of the proposed architecture with a conventional CDMA rake receiver in terms of the number of Walsh code channels. The result shows that our proposed architecture has a 12% and 18.6% reduction in gate count when the number of Walsh code channels is 4 and 7, respectively.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121963294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Pattern generation for verification of VHDL behavioral-level design 验证VHDL行为级设计的模式生成
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824096
Jong-Hyeon Kim, Seung-Kyu Park, Young-ho Seo, Dong-Wook Kim
{"title":"Pattern generation for verification of VHDL behavioral-level design","authors":"Jong-Hyeon Kim, Seung-Kyu Park, Young-ho Seo, Dong-Wook Kim","doi":"10.1109/APASIC.1999.824096","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824096","url":null,"abstract":"Design methodology has been changing from schematic-based design to HDL based-design. In HDL based-design, coding errors may exist and it takes much time to be found and corrected in design process. Thus an efficient method to verify the correctness of the coding itself is required. In this paper, we proposed a verification method for VHDL behavioral level design. VHDL coding is converted into CDFG and verification patterns are generated. Generated patterns are applied to VHDL design and the gold-unit. If there is difference in responses from VHDL design and gold-unit, coding error exists in VHDL design, and the proposed method detects and locates the coding error. Simulation result showed that the proposed method could verify the correctness of the design efficiently.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125548064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The low-area of new arc-tangent look-up table and a low overhead for CATV modem systems 新型切线查表面积小，有线电视调制解调器系统开销低
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824022
Young-Hoon Ban, Byung-Lok Choj, Jai-Chul Song
{"title":"The low-area of new arc-tangent look-up table and a low overhead for CATV modem systems","authors":"Young-Hoon Ban, Byung-Lok Choj, Jai-Chul Song","doi":"10.1109/APASIC.1999.824022","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824022","url":null,"abstract":"Makes possible a removal of the preamble for carrier recovery and symbol-timing recovery by storing a burst in memory with low overhead quaternary phase shift keying (QPSK) demodulation method which also effects frame efficiency improved by processed synchronization performance. In this paper, we propose the new algorithm for arc-tangent look-up table which transforms the input I, Q data by phase. This I, Q data plays an important role in demodulation and realises a demodulator with low-overhead by storing a burst in memory.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130924100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
IEEE 1284 softcore-implementation issues IEEE 1284软核实现问题
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824080
Myoung-Han Lee, Sun-Kyu Kim, Myoung-Sun Park, Yl-Seong Bae, P. Chung
{"title":"IEEE 1284 softcore-implementation issues","authors":"Myoung-Han Lee, Sun-Kyu Kim, Myoung-Sun Park, Yl-Seong Bae, P. Chung","doi":"10.1109/APASIC.1999.824080","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824080","url":null,"abstract":"In this paper, we present a re-usable softcore for the IEEE 1284 protocol for parallel data transmission. It consists of two parts. One is the firmware to cope with the IEEE-1284 protocol being executed in the processor and the other is the hardware engine to accelerate the basic communication mechanism. Using our evaluation system, it is verified that the designed core is fully compliant with the specification. Additionally, we show the results on the performance comparison between the compatibility and ECP modes of the IEEE-1284 standard.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123661152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel FPGA design of a high throughput rate adaptive prediction error filter 一种新型高吞吐率自适应预测误差滤波器的FPGA设计
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824063
Y. Hwang, Jih-Cheng Han
{"title":"A novel FPGA design of a high throughput rate adaptive prediction error filter","authors":"Y. Hwang, Jih-Cheng Han","doi":"10.1109/APASIC.1999.824063","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824063","url":null,"abstract":"In this paper we propose a novel adaptive prediction error filter design and implement it as a DSP core on FPGAs. The filter consists of a predictor and a Toeplitz solver. Previous ASIC design approaches often encountered problems such as unbalanced computing loads and extra data redirection circuit overheads. Therefore, we first reformulate the Schur algorithm and then derive an efficient systolic array designs capable of solving a size N Toeplitz matrix in every 2N cycles with each cycle equal to one MAC delay. The predictor design is implemented using the distributed arithmetic (DA) approach. The entire design is described in synthesizable VHDL code and fully parameterized with respect to the matrix size and word length. For the case of solving a tap 50 adaptive prediction error filter, we can achieve a clock rate of 40 MHz and a processing (symbol) rate as high as 60,976 matrix updates per second using four Xilinx 4044XL-3 FPGAs.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127923810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 0.7-1 Gb/s CMOS clock recovery circuit 一个0.7- 1gb /s的CMOS时钟恢复电路
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824086
Hui Wang, R. Nottenburg
{"title":"A 0.7-1 Gb/s CMOS clock recovery circuit","authors":"Hui Wang, R. Nottenburg","doi":"10.1109/APASIC.1999.824086","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824086","url":null,"abstract":"A 0.7-1 Gb/s clock recovery circuit is designed by ruing a 0.5 /spl mu/m digital CMOS process. It consists of a bang-bang type frequency detector (FD) to acquire frequency lock and a linear phase detector (PD) to acquire phase lock. The FD is able to reset itself upon frequency lock. Measured RMS jitter of the recovered clock is 7.4 ps at 1 GHz and 7 ps at 0.7 GHz. It is able to maintain a BER better than 10/sup -11/ for up to 140 missing transitions. It consumes 200 mW with a 5 V power supply.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115468708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and analysis of symmetric dual-layer spiral inductors for RF integrated circuits 射频集成电路对称双层螺旋电感的设计与分析
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824011
Sang-Gug Lee, G. Ihm, W. Song
{"title":"Design and analysis of symmetric dual-layer spiral inductors for RF integrated circuits","authors":"Sang-Gug Lee, G. Ihm, W. Song","doi":"10.1109/APASIC.1999.824011","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824011","url":null,"abstract":"An area efficient and symmetric dual-layer spiral inductor structure is proposed and evaluated in comparison with the conventional single-layer spiral inductors. Measurements show that, for a given silicon area, the dual-layer inductor provides nearly 4 time the inductance of the single-layer inductor, while the quality factor is up to 2 times higher. For the same amount of inductance the dual-layer inductors show comparable to higher quality factor depends on frequency of operation. This paper demonstrates that, contrary to the common understanding the dual-layer can be more useful for the RF integrated circuits than the conventional single-layered spiral inductors from the aspects of area efficiency and quality factor The proposed dual-layer inductor can also be used as a high-frequency choke.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114633133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 3 V 10 b 70 MHz digital-to-analog converter for video applications 用于视频应用的3v 10b70mhz数模转换器
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824059
Jin Park, Seung-Chul Lee, Seunghoon Lee
{"title":"A 3 V 10 b 70 MHz digital-to-analog converter for video applications","authors":"Jin Park, Seung-Chul Lee, Seunghoon Lee","doi":"10.1109/APASIC.1999.824059","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824059","url":null,"abstract":"This paper describes a 10 b 70 MHz CMOS digital-to-analog converter (DAC) for video applications. The proposed 10 b DAC is composed of a unit decoded matrix for 7 MSB's and a binary weighted array for 3 LSBs, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascode current sources and differential switches with the proposed new deglitching circuit improve dynamic performance. The fabricated and measured prototype DAC in a 0.8 um double-poly double-metal n-well CMOS process typically shows a spurious free dynamic range of 55 dB and a total harmonic distortion of -49 dB at a 3 V supply voltage and a 70 MHz update rate with a 120 mW power consumption. The measured differential and integral nonlinearities are /spl plusmn/0.69 LSB and /spl plusmn/0.79 LSB at a 10 b level, respectively.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124323275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A GHz I-Q quadrature signal generator using cellular oscillator network 一种基于蜂窝振荡器网络的GHz I-Q正交信号发生器
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824036
Sun-Mo Hwang, G. Moon, Seong-Ho Song
{"title":"A GHz I-Q quadrature signal generator using cellular oscillator network","authors":"Sun-Mo Hwang, G. Moon, Seong-Ho Song","doi":"10.1109/APASIC.1999.824036","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824036","url":null,"abstract":"The design of a GHz I-Q and Signal CMOS Generator using a Cellular Oscillator Network architecture is presented and analyzed. With its high speed for settling and easy frequency controllability, this I-Q signal generation method can be used in RF communication systems, where GHz range quadrature signals are needed. Also, a technique is presented for a sleeping mode with a small settling time. This model is simulated and proved with typical 3 V, 0.5 /spl mu/ CMOS N-well process parameters.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124981564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Realization of current-mode multifunction filters using multiple-output current conveyors 用多输出电流输送机实现电流型多功能滤波器
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI: 10.1109/APASIC.1999.824028
M. Higashimura, Y. Fukui
{"title":"Realization of current-mode multifunction filters using multiple-output current conveyors","authors":"M. Higashimura, Y. Fukui","doi":"10.1109/APASIC.1999.824028","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824028","url":null,"abstract":"This paper presents novel circuit configuration for realizing current-mode one-input and three-output type biquads using multiple-output current conveyors (MOCCIIs) and grounded passive elements. These circuits realize high-pass, band-pass and low-pass transfer functions simultaneously. By connecting output terminals, we can also realize bandstop and allpass transfer functions. The circuits use grounded capacitors, and have high output impedances which are suitable for current outputs. The cutoff frequency of the filter can be tuned independently of Q by the value of current gain K.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117241447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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