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APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems最新文献

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A 2.5Gb/s oversampling clock and data recovery circuit with frequency calibration technique 2.5Gb/s过采样时钟和数据恢复电路，采用频率校准技术
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems Pub Date : 2008-11-01 DOI: 10.1109/APCCAS.2008.4746280
K. P. Wu, Ching-Yuan Yang, Jung-Mao Lin
{"title":"A 2.5Gb/s oversampling clock and data recovery circuit with frequency calibration technique","authors":"K. P. Wu, Ching-Yuan Yang, Jung-Mao Lin","doi":"10.1109/APCCAS.2008.4746280","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746280","url":null,"abstract":"In this paper, a 2.5-Gb/s oversampling clock and data recovery (CDR) circuit with frequency calibration is realized for optical communication. The CDR circuit contains a fractional-N phase-locked loop (PLL), a delta-sigma modulator (DSM) and a data recovery circuit. The recovered clock is adjusted by the DSM for phase and frequency tuning, incorporating with the phase detector, when the incoming data rate changes. The CDR circuit is implemented with TSMC 0.18-um 1P6M CMOS technology. The simulation results show the proposed CDR circuit recovers the incoming data.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117292555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Generalized matrix method for efficient residue to decimal conversion 有效残数到十进制转换的广义矩阵法
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems Pub Date : 2008-11-01 DOI: 10.1109/APCCAS.2008.4746295
K. Gbolagade, S. Cotofana
{"title":"Generalized matrix method for efficient residue to decimal conversion","authors":"K. Gbolagade, S. Cotofana","doi":"10.1109/APCCAS.2008.4746295","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746295","url":null,"abstract":"In this paper, we present a matrix based method for efficient Residue to decimal conversion. First, we generalize a previously proposed technique that was restricted to 5-moduli set such that it becomes applicable to any RNS with the set of relatively prime integer moduli {mi}i=1,n. Next, we simplify the computing procedure by maximizing the utilization of the modulo-mi adders and multipliers present in the RNS functional units. For an n-digit RNS number X = (x1; x2; x3; ....; xn) the proposed method takes at most n iterations. Each iteration requires one parallel subtractions and 2 multiplications except the first one. This scheme results in an RNS to MRC with an asymptotic complexity, in terms of arithmetic operations, in the order of O(n), while the traditional MRC technique exhibits an asymptotic complexity in the order of O (n2). In particular, the utilization of our technique, for 3-moduli and 10-moduli RNS results in the reduction of the total number of arithmetic operations required by the conversion process with 13:33% and 66:05%, respectively, when compared to state of the art MRC.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123955410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Self-tuning PSM controller based on state machine 基于状态机的自整定PSM控制器
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems Pub Date : 2008-11-01 DOI: 10.1109/APCCAS.2008.4746170
Ping Luo, Zhaoji Li, Shaowei Zhen, Bo Zhang
{"title":"Self-tuning PSM controller based on state machine","authors":"Ping Luo, Zhaoji Li, Shaowei Zhen, Bo Zhang","doi":"10.1109/APCCAS.2008.4746170","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746170","url":null,"abstract":"A self-tuning pulse skip modulation (PSM) controller based on state machine is proposed in this paper. Four kinds of duty ratios are designed in the self-tuning PSM controller to balance the input energy and output energy. With which, the self-tuning PSM controller can make the power switch converter response quickly and the energy transfer better, as well as, avoid the real switching frequency entering into audible range with small output voltage ripple besides good stability and high efficiency. Analyses, simulations and experiments show the self-tuning PSM control technique based on the state machine is a good regulating mode for power converter.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125837888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low jitter DLL-based pulsewidth control loop with wide duty cycle adjustment 具有宽占空比调节的低抖动dll脉宽控制回路
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems Pub Date : 2008-11-01 DOI: 10.1109/APCCAS.2008.4746049
R. Weng, Chun-Yu Liu, Yun-Chih Lu
{"title":"A low jitter DLL-based pulsewidth control loop with wide duty cycle adjustment","authors":"R. Weng, Chun-Yu Liu, Yun-Chih Lu","doi":"10.1109/APCCAS.2008.4746049","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746049","url":null,"abstract":"A pulsewidth control loop (PWCL) based on a delay-locked loop (DLL) is presented in the paper. The duty cycle of the proposed PWCL can be adjusted from 10% to 90% in 10% step. The circuit is designed and simulated using TSMC 0.13 mum CMOS process. The operation frequency range is from 770 MHz to 1.43 GHz. The locking time of DLL is less than 15 ns within the operation frequency band. The power dissipation is 3 mW at 1.2 V voltage supply. The peak-to-peak jitter is less than 2 ps at an input clock frequency of 1.25 GHz while adjusting various duty cycles.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125869392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design of a green mode PWM control IC 绿色PWM控制IC的设计
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems Pub Date : 2008-11-01 DOI: 10.1109/APCCAS.2008.4746410
Hung-Da Hsu, T. Liang, Bin-Da Liu, Kai-Hui Chen
{"title":"Design of a green mode PWM control IC","authors":"Hung-Da Hsu, T. Liang, Bin-Da Liu, Kai-Hui Chen","doi":"10.1109/APCCAS.2008.4746410","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746410","url":null,"abstract":"To decrease the power consumption of a switching power supply, the most effective approach is to lower the switching frequency. Hence, the current mode pulse-width-modulation (PWM) controller used in a switching regulator must be capable of frequency modulation at light-load condition. The green mode circuit is designed in proposed current mode PWM control IC with the concept of off-time modulation. The switching frequency reduction and switch losses will be proportion to the load decrease at light-load condition. Also, the leading edge blanking (LEB), soft start, slope compensation, and over voltage protection (OVP) functions are integrated into the proposed chip.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129382621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Q-band bandpass filter designs in heterodyne receiver for radio astronomy 射电天文外差接收机q波段带通滤波器设计
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems Pub Date : 2008-11-01 DOI: 10.1109/APCCAS.2008.4745966
Yo-Shen Lin, Yu-Shu Hsieh, Yuh-Jing Hwang, Chau-Ching Chiong
{"title":"Q-band bandpass filter designs in heterodyne receiver for radio astronomy","authors":"Yo-Shen Lin, Yu-Shu Hsieh, Yuh-Jing Hwang, Chau-Ching Chiong","doi":"10.1109/APCCAS.2008.4745966","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4745966","url":null,"abstract":"This paper presents two Q-band bandpass filter designs that are targeted for application in the Atacama large millimeter-wave and submillimeter-wave array (ALMA) radio telescope. The bandpass filter is required to reject the lower side band from 15.2~29 GHz and retain minimum loss across the passband of 31.3~45 GHz. The bandpass filter based on WR22 waveguide is first presented. Specifically, the measured in-band insertion loss is around 0.4 dB, and the rejection of lower sideband is better than 34 dB. To further reduce the circuit size and to ease the integration with other MMICs in the receiver, a planar filter design based on GaAs process is also demonstrated. It will be applied to the multi-chip module version of the heterodyne receiver design to achieve more compact module size.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129460776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
State-observer-based approach for identification and monitoring of complex dynamical networks 基于状态观测器的复杂动态网络辨识与监测方法
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems Pub Date : 2008-11-01 DOI: 10.1109/APCCAS.2008.4746244
Hao Liu, Guoping Jiang, Chunxia Fan
{"title":"State-observer-based approach for identification and monitoring of complex dynamical networks","authors":"Hao Liu, Guoping Jiang, Chunxia Fan","doi":"10.1109/APCCAS.2008.4746244","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746244","url":null,"abstract":"Recently, lots of work investigated the geometry features, synchronization and control of complex dynamical networks provided with certain topology. But in the real life, the exact topology of a network is often uncertain. In this paper, a new approach for approximately identifying the topology of a complex network is proposed based on the state observer design only using a scalar coupling signal. Unlike the other methods assuming that the dynamics of the network can be described by a linear stochastic model, or using states of the nodes to design an adaptive observer, we use the output variable to design a state observer to approximately identify the topology of a complex network and monitor any changes of the topology structure.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128458245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
GPU accelerated fast FEM deformation simulation GPU加速快速有限元变形模拟
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems Pub Date : 2008-11-01 DOI: 10.1109/APCCAS.2008.4746096
Youquan Liu, Shaohui Jiao, Wen Wu, S. De
{"title":"GPU accelerated fast FEM deformation simulation","authors":"Youquan Liu, Shaohui Jiao, Wen Wu, S. De","doi":"10.1109/APCCAS.2008.4746096","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746096","url":null,"abstract":"In this paper we present a general FEM (finite element method) solution that enables fast dynamic deformation simulation on the newly available GPU (graphics processing unit) hardware with compute unified device architecture (CUDA) from NVIDIA. CUDA-enabled GPUs harness the power of 128 processors which allow data parallel computations. Compared to the previous GPGPU, it is significantly more flexible with a C language interface. We not only implement FEM deformation computation algorithms with CUDA but also analyze the performance in detail. Our test results indicate that the GPU with CUDA enables about 4 times speedup for FEM deformation computation on an Intel(R) Core 2 Quad 2.0 GHz machine with GeForce 8800 GTX.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129614749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Low energy CMOS true single phase power supply clocking adiabatic differential cascode voltage switch logic circuit 低功耗CMOS真单相电源时钟绝热差分级联电压开关逻辑电路
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems Pub Date : 2008-11-01 DOI: 10.1109/APCCAS.2008.4746183
José C. García, J. Montiel-Nelson, S. Nooshabadi
{"title":"Low energy CMOS true single phase power supply clocking adiabatic differential cascode voltage switch logic circuit","authors":"José C. García, J. Montiel-Nelson, S. Nooshabadi","doi":"10.1109/APCCAS.2008.4746183","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746183","url":null,"abstract":"This paper presents the design of a highly energy efficient CMOS adiabatic driver (ob-driver). The proposed ob-driver uses an output stage with two inverters driven by a pre-driver circuit consisting of two differential cascode voltage switch (DCVS) logic cells. When implemented on a 0.13 mum CMOS 1.2V technology, under the large capacitive loading condition, ob-driver performs better than the reference adiabatic circuit (sp-driver) in terms of the energy-delay product (34%), with active area which is only (9%) higher.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129632705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
CDTA-based current limiters and applications 基于cdta的电流限制器及其应用
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems Pub Date : 2008-11-01 DOI: 10.1109/APCCAS.2008.4746209
T. Pukkalanun, W. Tangsrirat
{"title":"CDTA-based current limiters and applications","authors":"T. Pukkalanun, W. Tangsrirat","doi":"10.1109/APCCAS.2008.4746209","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746209","url":null,"abstract":"In this paper, a synthesis of analog current limiter (CL) building blocks based on a current differencing transconductance amplifier (CDTA) is proposed. The breakpoint and the slope of the resulting transfer characteristic obtained from the proposed CDTA-based CLs are electronically programmable through the external bias currents. To demonstrate versatility of the proposed electronically tunable CLs, some nonlinear applications to programmable current-mode precision full-wave rectifier and piecewise-linear function approximation generators are also presented. SPICE simulations confirm the effectiveness of the proposed circuits.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127099804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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