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4th international joint conference on pattern recognition 第四届模式识别国际联合会议
Iee Journal on Computers and Digital Techniques Pub Date : 1979-04-01 DOI: 10.1049/IJ-CDT:19790013
C. Verhagen
{"title":"4th international joint conference on pattern recognition","authors":"C. Verhagen","doi":"10.1049/IJ-CDT:19790013","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790013","url":null,"abstract":"","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121139756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Design of counter registers 计数器寄存器的设计
Iee Journal on Computers and Digital Techniques Pub Date : 1979-04-01 DOI: 10.1049/IJ-CDT.1979.0015
Ferdynand Wagner
{"title":"Design of counter registers","authors":"Ferdynand Wagner","doi":"10.1049/IJ-CDT.1979.0015","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1979.0015","url":null,"abstract":"The paper describes a method of designing counter registers. Two important features of the method are that it produces a minimal design and that it is guaranteed to avoid jamming. The method may be applied to the synthesis of any counter registers used, for example, as binary-sequence generators, word generators, counters, pseudorandom binary-sequence generators etc. The paper contains examples which demonstrate the design procedure, and gives some results relating to minimal counter registers.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121102333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
European solid-state circuits conference 欧洲固态电路会议
Iee Journal on Computers and Digital Techniques Pub Date : 1979-02-01 DOI: 10.1049/IJ-CDT:19790007
J. Gosling
{"title":"European solid-state circuits conference","authors":"J. Gosling","doi":"10.1049/IJ-CDT:19790007","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790007","url":null,"abstract":"","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"76 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116350292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
Determination of the set of the irredundant modulo-2 sums-of-products expressions of a logic function 逻辑函数的无冗余模-2积和表达式集合的确定
Iee Journal on Computers and Digital Techniques Pub Date : 1979-02-01 DOI: 10.1049/IJ-CDT:19790002
Z. Lotfi, D. Aoulad-Syad, A. Tosser
{"title":"Determination of the set of the irredundant modulo-2 sums-of-products expressions of a logic function","authors":"Z. Lotfi, D. Aoulad-Syad, A. Tosser","doi":"10.1049/IJ-CDT:19790002","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790002","url":null,"abstract":"An overlapping equation written with the exclusive-OR operator is used for the determination of the irredundant mod-2 sums-of-products expressions of a logical function.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131246269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Compression of binary images by stroke encoding 用笔画编码压缩二值图像
Iee Journal on Computers and Digital Techniques Pub Date : 1979-02-01 DOI: 10.1049/IJ-CDT.1979.0010
I. D. Judd
{"title":"Compression of binary images by stroke encoding","authors":"I. D. Judd","doi":"10.1049/IJ-CDT.1979.0010","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1979.0010","url":null,"abstract":"The application of digital image systems to document handling in offices is currently limited by the high data transmission and storage costs. This paper describes a new method for encoding binary images of text or line drawings that achieves a high degree of data compaction in return for a small loss of fidelity. Typically, the compressed data stream is only two-thirds of the size of that produced by a reference algorithm employing a 3-pel predictor and a highly sophisticated error encoder. The input image is first processed by a thinning algorithm to extract the centrelines of the strokes that form the characters and lines. A tracking algorithm then connects neighbouring black picture elements into chains whose shapes and positions are encoded to produce the compressed data stream. Outline hardware implementations for the thinning and tracking algorithms are given.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131166294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Zone management processor: a module for generating surfaces in raster-scan colour displays 区域管理处理器:用于在光栅扫描彩色显示器中生成表面的模块
Iee Journal on Computers and Digital Techniques Pub Date : 1979-02-01 DOI: 10.1049/IJ-CDT:19790005
R. L. Grimsdale, A. A. Hadjiaslanis, P. Willis
{"title":"Zone management processor: a module for generating surfaces in raster-scan colour displays","authors":"R. L. Grimsdale, A. A. Hadjiaslanis, P. Willis","doi":"10.1049/IJ-CDT:19790005","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790005","url":null,"abstract":"The zone management processor is a new display device for use in raster-scan display systems, its purpose being to generate areas with distinctive hue and luminance. The device is particularly useful for the display of solid objects and perspective views of scenes with the image being portrayed as a collection of surfaces. An image is normally produced by a multiprocessor system consisting of a number of these processors. The boundary edges of surfaces produced by the processors may be straight or curved. Mutual interaction of several processors results in correct presentation of surfaces obscured by other surfaces closer to the viewer. The system described operates to 625-line raster-scan colour television standards. The arrangement is especially suitable for the display of scenes changing rapidly in real time. A number of techniques for improvement of the static and dynamic quality of the images are described.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130820507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Book review: Theory and Design of Switching Circuits 书评:开关电路的理论与设计
Iee Journal on Computers and Digital Techniques Pub Date : 1979-02-01 DOI: 10.1049/ij-cdt.1979.0006
R. L. Grimsdale
{"title":"Book review: Theory and Design of Switching Circuits","authors":"R. L. Grimsdale","doi":"10.1049/ij-cdt.1979.0006","DOIUrl":"https://doi.org/10.1049/ij-cdt.1979.0006","url":null,"abstract":"","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126839903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
V.L.S.I. and the digital-system design revolution vls和数字系统设计革命
Iee Journal on Computers and Digital Techniques Pub Date : 1979-02-01 DOI: 10.1049/IJ-CDT:19790001
S. Hollock
{"title":"V.L.S.I. and the digital-system design revolution","authors":"S. Hollock","doi":"10.1049/IJ-CDT:19790001","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790001","url":null,"abstract":"","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131032609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparison of universal logic gates with NAND and NOR gates in the realisation of functions of three variables 通用逻辑门与NAND门、NOR门在实现三变量函数中的比较
Iee Journal on Computers and Digital Techniques Pub Date : 1979-02-01 DOI: 10.1049/IJ-CDT.1979.0004
S. Hurst, N. P. Pflaeger
{"title":"Comparison of universal logic gates with NAND and NOR gates in the realisation of functions of three variables","authors":"S. Hurst, N. P. Pflaeger","doi":"10.1049/IJ-CDT.1979.0004","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1979.0004","url":null,"abstract":"This report furthers earlier work of, in particular, Hellerman, who catalogued the minimum number of NOR and NAND elements necessary to realise all 223 logic functions of three independent binary input variables. Here we consider the use of universal logic elements rather than NOR and NAND, and derive corresponding statistical and detailed information when the former are used for random logic purposes.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123208423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Anatomy of Boolean-function simplification 布尔函数化简的解剖
Iee Journal on Computers and Digital Techniques Pub Date : 1979-02-01 DOI: 10.1049/IJ-CDT:19790003
P. Besslich
{"title":"Anatomy of Boolean-function simplification","authors":"P. Besslich","doi":"10.1049/IJ-CDT:19790003","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790003","url":null,"abstract":"The existing methods for the simplification of Boolean functions are usually classified according to their mathematical background (e.g. consenus method) or their procedural tools (e.g. diagram methods) or are named in honour of scientists (e.g. Quine-McCluskey method). To make the methods more transparent, with respect to the judgment of their effectiveness in solving practical problems, it is suggested that they be classified according to the strategy of prime implicant generation. It is shown that the known methods can be assigned to one of the following basic strategies for the generation of prime implicants: (a) building-up from smaller implicants; (b) expansion of the function along literals or variables; (c) separation of the vector space into 1-subspaces and O-subspaces; (d) systematic inspection of all possible implicants; (e) heuristic methods. The strategy is shown to be a governing factor for the effectiveness of minimisation procedures, particularly if, owing to the complexity of the problems, only approximately minimal solutions can be obtained.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125726227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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