2013 International Conference on Field-Programmable Technology (FPT)最新文献

Design and optimization of heterogeneous tree-based FPGA using 3D technology 基于3D技术的异构树FPGA设计与优化

2013 International Conference on Field-Programmable Technology (FPT) Pub Date : 2013-12-09 DOI: 10.1109/FPT.2013.6718380

V. Pangracious, Z. Marrakchi, H. Mehrez

引用次数: 0

Correction to “Graph Minor Approach for Application Mapping on CGRAs” 更正“在CGRAs上进行应用绘图的小图方法”

2013 International Conference on Field-Programmable Technology (FPT) Pub Date : 2013-12-01 DOI: 10.1109/FPT.2013.6718431

Liang Chen, T. Mitra

引用次数: 1

Application-specific customisation of market data feed arbitration 特定于应用程序的定制市场数据馈送仲裁

2013 International Conference on Field-Programmable Technology (FPT) Pub Date : 2013-12-01 DOI: 10.1109/FPT.2013.6718377

S. Denholm, Hiroaki Inoue, Takashi Takenaka, W. Luk

{"title":"Application-specific customisation of market data feed arbitration","authors":"S. Denholm, Hiroaki Inoue, Takashi Takenaka, W. Luk","doi":"10.1109/FPT.2013.6718377","DOIUrl":"https://doi.org/10.1109/FPT.2013.6718377","url":null,"abstract":"Messages are transmitted from financial exchanges to update their members about changes in the market. As UDP packets are used for message transmission, members subscribe to two identical message feeds from the exchange to lower the risk of message loss or delay. As financial trades can be time sensitive, low latency arbitration between these market data feeds is of particular importance. Members must either provide generic arbitration for all of their financial applications, increasing latency, or arbitrate within each application which wastes resources and scales poorly. We present a reconfigurable accelerated approach for market feed arbitration operating at the network level. Multiple arbitrators can operate within a single FPGA to output customised feeds to downstream financial applications. Application-specific customisations are supported by each core, allowing different market feed messaging protocols, windowing operations and message buffering parameters. We model multiple-core arbitration and explore the scalability and performance improvements within and between cores. We demonstrate our design within a Xilinx Virtex-6 FPGA using the NASDAQ TotalView-ITCH 4.1 messaging standard. Our implementation operates at 16Gbps throughput, and with resource sharing, supports 12 independent cores, 33% more than simple core replication. A 56ns (7 clock cycles) windowing latency is achieved, 2.6 times lower than a hardware-accelerated CPU approach.","PeriodicalId":344469,"journal":{"name":"2013 International Conference on Field-Programmable Technology (FPT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127116781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A high-throughput FPGA architecture for parallel connected components analysis based on label reuse 一种基于标签复用的并行连接元件分析高吞吐量FPGA架构

2013 International Conference on Field-Programmable Technology (FPT) Pub Date : 2013-12-01 DOI: 10.1109/FPT.2013.6718372

M. Klaiber, D. Bailey, Silvia Ahmed, Y. Baroud, S. Simon

引用次数: 22

Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting 基于自适应部分重路由的fpga随机延迟可变性研究

2013 International Conference on Field-Programmable Technology (FPT) Pub Date : 2013-12-01 DOI: 10.1109/FPT.2013.6718362

Zhenyu Guan, Justin S. J. Wong, S. Chaudhuri, G. Constantinides, P. Cheung

引用次数: 5

Quantum FPGA architecture design 量子FPGA架构设计

2013 International Conference on Field-Programmable Technology (FPT) Pub Date : 2013-12-01 DOI: 10.1109/FPT.2013.6718386

Jialin Chen, Lingli Wang, Bin Wang

引用次数: 2

Implementation of a highly scalable blokus duo solver on FPGA 在FPGA上实现一个高度可扩展的blokus二解器

2013 International Conference on Field-Programmable Technology (FPT) Pub Date : 2013-12-01 DOI: 10.1109/FPT.2013.6718423

Chester Liu

引用次数: 4

StML: Bridging the gap between FPGA design and HDL circuit description 弥合FPGA设计和HDL电路描述之间的差距

2013 International Conference on Field-Programmable Technology (FPT) Pub Date : 2013-12-01 DOI: 10.1109/FPT.2013.6718366

Dustin Peterson, O. Bringmann, Thomas Schweizer, W. Rosenstiel

{"title":"StML: Bridging the gap between FPGA design and HDL circuit description","authors":"Dustin Peterson, O. Bringmann, Thomas Schweizer, W. Rosenstiel","doi":"10.1109/FPT.2013.6718366","DOIUrl":"https://doi.org/10.1109/FPT.2013.6718366","url":null,"abstract":"FPGA circuit implementation is a unidirectional and time-consuming process. Existing approaches like the incremental synthesis try to shorten it, but still need to execute the whole flow for a changed circuit partition. Other approaches circumvent process stages by providing bidirectional mappings between their results. In this paper we propose an approach to provide a bidirectional link between an FPGA design and its HDL code. This link enables the circumvention of the most time-consuming stages (synthesis, mapping, placing, routing) of the FPGA circuit implementation. We implemented our approach in a Java-based EDA tool library, called Static Mapping Library (StML). We demonstrate its applicability by means of hardware debugging and an RTL-based injection of permanent faults, built on top of the StML. Experimental results illustrate that a mapping coverage between 98.5%-100.0% can be obtained, which substantiates the feasibility of this approach. Further experiments illustrate a controllable tradeoff between area overhead, circuit granularity and mapping granularity. With the finest mapping granularity, the area overhead has been between 1.8% and 60.2% for RTL-based circuits. The speedup of the proposed fault injection method has been estimated to be up to 6x for the tested circuits.","PeriodicalId":344469,"journal":{"name":"2013 International Conference on Field-Programmable Technology (FPT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129707987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

ZCluster: A Zynq-based Hadoop cluster ZCluster:基于zynq的Hadoop集群

2013 International Conference on Field-Programmable Technology (FPT) Pub Date : 2013-12-01 DOI: 10.1109/FPT.2013.6718411

Zhongduo Lin, P. Chow

引用次数: 48

A connection-based router for FPGAs 用于fpga的基于连接的路由器

2013 International Conference on Field-Programmable Technology (FPT) Pub Date : 2013-12-01 DOI: 10.1109/FPT.2013.6718378

Elias Vansteenkiste, Karel Bruneel, D. Stroobandt

引用次数: 3