2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献_第9页

Exploiting assertions mining and fault analysis to guide RTL-level approximation 利用断言挖掘和故障分析来指导rtl级逼近

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10136949

A. Bosio, Samuele Germiniani, G. Pravadelli, Marcello Traiola

{"title":"Exploiting assertions mining and fault analysis to guide RTL-level approximation","authors":"A. Bosio, Samuele Germiniani, G. Pravadelli, Marcello Traiola","doi":"10.23919/DATE56975.2023.10136949","DOIUrl":"https://doi.org/10.23919/DATE56975.2023.10136949","url":null,"abstract":"Approximate Computing (AxC) paradigm was introduced to achieve higher power efficiency, lower area and better performances w.r.t. a “classical” computing system at the cost of a degraded, but still acceptable, output accuracy [1]. AxC can be applied at several abstraction levels of a given computing system: from circuit to algorithm [1], leading to a wide design exploration space that quickly became the bottleneck for successfully deploying AxC. Indeed, the literature proposes many works to automatically trade-off between output accuracy and performances [2]. However, most of them lack the capability to identify resilient elements (e.g, HW component, HDL statements, etc.) of the design to be approximated. Consequently, exploring the design for AxC generally results in a long and tedious procedure. Existing approaches generate approximate variants of the Design Under Exploration (DUE). Every variant is then executed/simulated in order to determine the accuracy degradation [3], which depends on the application and requires a specific metric to be computed (e.g., similarity index, hamming distance, etc.).","PeriodicalId":340349,"journal":{"name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124154745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MECALS: A Maximum Error Checking Technique for Approximate Logic Synthesis 一种近似逻辑综合的最大误差检测技术

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10136950

Chang Meng, Jiajun Sun, Yuqi Mai, Weikang Qian

引用次数: 0

Reduce: A Framework for Reducing the Overheads of Fault-Aware Retraining Reduce:一个减少故障感知再培训开销的框架

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10137268

Muhammad Abdullah Hanif, M. Shafique

引用次数: 0

Memristor-Spikelearn: A Spiking Neural Network Simulator for Studying Synaptic Plasticity under Realistic Device and Circuit Behaviors 忆阻器- spike - learn:一种用于研究现实器件和电路行为下突触可塑性的spike神经网络模拟器

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10136938

Yuming Liu, A. Yanguas-Gil, Sandeep Madireddy, Yanjing Li

引用次数: 0

Two-Stream Neural Network for Post-Layout Waveform Prediction 用于布局后波形预测的双流神经网络

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10137286

Sanghwi Kim, Hyejin Shin, Hyunkyu Kim

引用次数: 0

Exploration of Decision Sub-Network Architectures for FPGA-based Dynamic DNNs 基于fpga的动态dnn决策子网络体系结构研究

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10137302

Anstasios Dimitriou, Mingyu Hu, Jonathon S. Hare, G. Merrett

{"title":"Exploration of Decision Sub-Network Architectures for FPGA-based Dynamic DNNs","authors":"Anstasios Dimitriou, Mingyu Hu, Jonathon S. Hare, G. Merrett","doi":"10.23919/DATE56975.2023.10137302","DOIUrl":"https://doi.org/10.23919/DATE56975.2023.10137302","url":null,"abstract":"Dynamic Deep Neural Networks (DNNs) can achieve faster execution and less computationally intensive inference by spending fewer resources on easy to recognise or less informative parts of an input. They make data-dependent decisions, which strategically deactivate a model's components, e.g. layers, channels or sub-networks. However, dynamic DNNs have only been explored and applied on conventional computing systems ($text{CPU} +text{GPU}$)) and programmed with libraries designed for static networks, limiting their effects. In this paper, we propose and explore two approaches for efficiently realising the sub-networks that make these decisions on FPGAs. A pipeline approach targets the use of the existing hardware to execute the sub-network, while a parallel approach uses dedicated circuitry for it. We explore the performance of each using the BranchyNet early exit approach on LeNet-5, and evaluate on a Xilinx ZCU106. The pipeline approach is 36% faster than a desktop CPU. It consumes 0.51 mJ per inference, 16x lower than a non-dynamic network on the same platform and 8x lower than an Nvidia Jetson Xavier NX. The parallel approach executes 17% faster than the pipeline approach when on dynamic inference no early exits are taken, but incurs an increase in energy consumption of 28%.","PeriodicalId":340349,"journal":{"name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115884072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

GraphIte: Accelerating Iterative Graph Algorithms on ReRAM Architectures via Approximate Computing 石墨:通过近似计算加速ReRAM架构上的迭代图算法

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10137001

Dwaipayan Choudhury, A. Kalyanaraman, P. Pande

引用次数: 0

Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry 缩小合成差距:FPGA的学术合成正在赶上工业界

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10137310

Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, A. Mishchenko, J. Greene, J. Wawrzynek

{"title":"Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry","authors":"Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, A. Mishchenko, J. Greene, J. Wawrzynek","doi":"10.23919/DATE56975.2023.10137310","DOIUrl":"https://doi.org/10.23919/DATE56975.2023.10137310","url":null,"abstract":"Historically, open-source FPGA synthesis and technology mapping tools have been considered far inferior to industry-standard tools. We show that this is no longer true. Improvements in recent years to Yosys (Verilog elaborator) and ABC (technology mapper) have resulted in substantially better performance, evident in both the reduction of area utilization and the increase in the maximum achievable clock frequency. More specifically, we describe how ABC9 — a set of feature additions to ABC — was integrated into Yosys upstream and available in the latest version. Technology mapping now has a complete view of the circuit, including support for hard blocks (e.g., carry chains) and multiple clock domains for timing-aware mapping. We demonstrate how these improvements accumulate in dramatically better synthesis results, with Yosys-ABC9 reducing the delay gap from 30% to 0% on a commercial FPGA target for the commonly used VTR benchmark, thus matching Vivado's performance in terms of maximum clock frequency. We also measured the performance on a selection of circuits from OpenCores as well as literature, comparing the results produced by Vivado, Yosys-ABC1 (existing work), and the proposed Yosys-ABC9 integration.","PeriodicalId":340349,"journal":{"name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116393995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware and Software Support for Mixed Precision Computing: a Roadmap for Embedded and HPC Systems 混合精确计算的硬件和软件支持:嵌入式和高性能计算系统的路线图

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10137092

W. Fornaciari, G. Agosta, Daniele Cattaneo, Lev Denisov, Andrea Galimberti, Gabriele Magnani, Davide Zoni

引用次数: 0

Using High-Level Synthesis to model System Verilog procedural timing controls 使用高级综合建模系统Verilog程序定时控制

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2023-04-01 DOI: 10.23919/DATE56975.2023.10136907

Luca Ezio Pozzoni, Fabrizio Ferrandi, Loris Mendola, Alfio Antonino Palazzo, Francesco Pappalardo

{"title":"Using High-Level Synthesis to model System Verilog procedural timing controls","authors":"Luca Ezio Pozzoni, Fabrizio Ferrandi, Loris Mendola, Alfio Antonino Palazzo, Francesco Pappalardo","doi":"10.23919/DATE56975.2023.10136907","DOIUrl":"https://doi.org/10.23919/DATE56975.2023.10136907","url":null,"abstract":"In modern SoC designs, digital components' development and verification processes often depend on the component's interactions with other digital and analog modules on the same die. While designers can rely on a wide range of tools and practices for validating fully-digital models, porting the same workflow to mixed models' development requires significant efforts from the designers. A common practice is to use Real Number Modeling techniques to generate HDL-based behavioral models of analog components to efficiently simulate mixed models using only event-based simulations rather than Analog Mixed Signals (AMS) simulations. However, some of these models' language features are not synthesizable with existing synthesis tools, requiring additional efforts from the designers to generate post-tapeout prototypes. This paper presents a methodology for transforming some non-synthesizable System Verilog language features related to timing controls into functionally-equivalent synthesizable Verilog constructs. The resulting synthesizable models replicate their respective RNMs' behavior while explicitly managing delay controls and event expressions. The RNMs are first transformed using the MLIR framework and then synthesized with open-source HLS tools to obtain FPGA-synthesizable Verilog models.","PeriodicalId":340349,"journal":{"name":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114295036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0