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2017 International Symposium on Signals, Circuits and Systems (ISSCS)最新文献

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Secure scan chain using a phase locking authentication technique 使用相位锁定认证技术的安全扫描链
2017 International Symposium on Signals, Circuits and Systems (ISSCS) Pub Date : 2017-07-01 DOI: 10.1109/ISSCS.2017.8034910
D. Richard, R. Rashidzadeh, M. Ahmadi
{"title":"Secure scan chain using a phase locking authentication technique","authors":"D. Richard, R. Rashidzadeh, M. Ahmadi","doi":"10.1109/ISSCS.2017.8034910","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034910","url":null,"abstract":"Scan is a widely used DfT (Design for Testing) technique for digital circuits, which provides a high observability and controllability. However, scan architectures can be used as a powerful tool to attack integrated circuits and extract sensitive information stored in the hardware. With the advent of 3D stacked ICs, it has become essential to implement a robust security measure to prevent scan-based attacks. In this work, a phase locking solution is presented to secure the scan architecture. A Phase Locked Loop (PLL) is utilized to authenticate the tester and provide access to the scan chain. The proposed scheme is dynamic and supports different authentication requirements for different layers in a 3D stacked IC without increasing the area overhead.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122618059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A frequency transformation based real frequency design approach for dual-band matching 一种基于频率变换的双频段匹配实频率设计方法
2017 International Symposium on Signals, Circuits and Systems (ISSCS) Pub Date : 2017-07-01 DOI: 10.1109/ISSCS.2017.8034909
A. Aksen, S. Yildiz, S. Yarman
{"title":"A frequency transformation based real frequency design approach for dual-band matching","authors":"A. Aksen, S. Yildiz, S. Yarman","doi":"10.1109/ISSCS.2017.8034909","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034909","url":null,"abstract":"This work describes a real frequency design approach for dual-band matching networks. The proposed design technique employs a direct low-pass to dual pass band frequency transformation in the scattering based real frequency design of transformer free double band matching filters. For prescribed matching pass-bands, the parameters of dual-band frequency transformation are also iterated to enhance the matching band control in the nonlinear optimization process. A dual band matching network design example is presented to illustrate the application of the design approach.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124568344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 200°C general purpose rail-to-rail complementary input class-AB operational amplifier for high temperature applications 200°C通用轨对轨互补输入ab类运算放大器，适用于高温应用
2017 International Symposium on Signals, Circuits and Systems (ISSCS) Pub Date : 2017-07-01 DOI: 10.1109/ISSCS.2017.8034901
L. Stoica, R. Ghandi, Cheng-Po Chen, V. Solomko
{"title":"A 200°C general purpose rail-to-rail complementary input class-AB operational amplifier for high temperature applications","authors":"L. Stoica, R. Ghandi, Cheng-Po Chen, V. Solomko","doi":"10.1109/ISSCS.2017.8034901","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034901","url":null,"abstract":"This paper covers the design and testing of an operational amplifier (opamp) used in a high temperature signal conditioning unit for integration with temperature and strain gauge sensors. The opamp was designed and fabricated in a 1 µm CMOS Silicon-on-Insulator (SOI) process and has been characterized up to 300°C. The measurement results at 200°C are showing a DC open-loop gain of 100dB, an offset voltage of 1mV, an input bias current of ±15pA, a common mode input range (CMIR) of [0–5]V and a unity gain frequency of 3.2MHz. The opamp has a size of 687µm × 218µm and draws a current of 550µA from a 5V supply. The opamp was used to design an instrumentation amplifier (IA) with a gain of 225 at 200°C.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127746853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An FPGA oprimization of a multiple resolution architecture for LDR to HDR image conversion 用于LDR到HDR图像转换的多分辨率架构的FPGA优化
2017 International Symposium on Signals, Circuits and Systems (ISSCS) Pub Date : 2017-07-01 DOI: 10.1109/ISSCS.2017.8034902
Carmine Cappetta, G. Licciardo, L. Di Benedetto
{"title":"An FPGA oprimization of a multiple resolution architecture for LDR to HDR image conversion","authors":"Carmine Cappetta, G. Licciardo, L. Di Benedetto","doi":"10.1109/ISSCS.2017.8034902","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034902","url":null,"abstract":"An architecture capable of performing the inverse Tone Mapping to convert a Low Dynamic Range image into a High Dynamic Range one is proposed. The proposed image processor is specifically designed for a Field Programmable Gate Array implementation. The design exploits the presence of specific blocks in the Field Programmable Logic board, dedicated to the implementation of memories, in order to develop an efficient implementation to process images having a resolution up to 4K UHDTV. The proposed implementation is developed avoiding frame buffers to obtain a design showing low power and a reduced area, in addition to a real-time processing of the image up to Full-HD frames. The proposed scheme achieves state-of-the-art performances and is a lot more flexible than previously developed single resolution architectures.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133521129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A ±2m°C linearity silicon temperature sensor ±2m°C线性硅温度传感器
2017 International Symposium on Signals, Circuits and Systems (ISSCS) Pub Date : 2017-07-01 DOI: 10.1109/ISSCS.2017.8034948
Stefan Marinca, Gabriel Banarie, Viorel Bucur, M. Bodea
{"title":"A ±2m°C linearity silicon temperature sensor","authors":"Stefan Marinca, Gabriel Banarie, Viorel Bucur, M. Bodea","doi":"10.1109/ISSCS.2017.8034948","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034948","url":null,"abstract":"Linearity of known silicon-based temperature sensors is limited by Early voltage effects [1]. A highly linear temperature sensor based on the base-emitter voltage difference of two bipolar transistors operating at different collector current densities with forward and reverse Early voltage compensation is presented. As it is demonstrated here, the linearity of such a temperature sensor may be increased significantly when compared to uncompensated architectures of silicon-based temperature sensors.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116954250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Image resizing in the compressed domain 在压缩域中调整图像大小
2017 International Symposium on Signals, Circuits and Systems (ISSCS) Pub Date : 2017-07-01 DOI: 10.1109/ISSCS.2017.8034942
J. Mukhopadhyay
{"title":"Image resizing in the compressed domain","authors":"J. Mukhopadhyay","doi":"10.1109/ISSCS.2017.8034942","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034942","url":null,"abstract":"Image resizing is used to convert an image of a given size to one of a different size. There exist different algorithms for resizing an image both in the spatial domain, as well as in the frequency domain where it is stored in compressed form. There are certain advantages of performing the resizing operation directly in the compressed domain. First, it saves the computational overhead of inverse and forward transforms. Next, by exploiting various properties of the transform domain, it is possible to design efficient fast algorithms providing good quality reconstructed image in the spatial domain. In this paper, we review a few algorithms for resizing an image by arbitrary sizes and provide a brief comparison of their performances.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131051969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Concepts and developments of an wearable system - an IoT approach 可穿戴系统的概念和发展-物联网方法
2017 International Symposium on Signals, Circuits and Systems (ISSCS) Pub Date : 2017-07-01 DOI: 10.1109/ISSCS.2017.8034922
D. Dobrea, Monica-Claudia Dobrea
{"title":"Concepts and developments of an wearable system - an IoT approach","authors":"D. Dobrea, Monica-Claudia Dobrea","doi":"10.1109/ISSCS.2017.8034922","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034922","url":null,"abstract":"This paper presents the concepts and the development process of a new and innovative wearable system able both to track the position and to analyze the movements of the head. This wearable system was developed as a main platform for a large class of applications in fields like: biomedical, medical, entertainment, military, automotive, consumer field etc. In the proposed system, the head position and movements are acquired in non-contact mode and by using some smart clothes that embed several capacitive sensors in the collar. The entire system was developed to be ultralow power and easy cloud-connected.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134079856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Amplification, feedback, and sub-biasing: Applying analog techniques to high-speed, low-power digital CMOS circuits 放大、反馈和次偏置:将模拟技术应用于高速、低功耗的数字CMOS电路
2017 International Symposium on Signals, Circuits and Systems (ISSCS) Pub Date : 2017-07-01 DOI: 10.1109/ISSCS.2017.8034947
D. Foty
{"title":"Amplification, feedback, and sub-biasing: Applying analog techniques to high-speed, low-power digital CMOS circuits","authors":"D. Foty","doi":"10.1109/ISSCS.2017.8034947","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034947","url":null,"abstract":"Analog and digital circuit design architectures are usually regarded as being separate spheres - with very different objectives, and thus consequently with very different methods of approaching the design challenges.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116839618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.2-pJ/bit 10-Gb/s forwarded-clock serial-link transceiver for IoE applications 用于IoE应用的2.2 pj /bit 10gb /s前向时钟串行链路收发器
2017 International Symposium on Signals, Circuits and Systems (ISSCS) Pub Date : 2017-07-01 DOI: 10.1109/ISSCS.2017.8034899
Mohamed El-Badry, M. El-Fiky, Aya Yasser, Ahmed G. Shehata, Mostafa El-Sayeh, A. Sallam, Mostafa Hagras, Ahmed Abdelati, S. Ibrahim
{"title":"A 2.2-pJ/bit 10-Gb/s forwarded-clock serial-link transceiver for IoE applications","authors":"Mohamed El-Badry, M. El-Fiky, Aya Yasser, Ahmed G. Shehata, Mostafa El-Sayeh, A. Sallam, Mostafa Hagras, Ahmed Abdelati, S. Ibrahim","doi":"10.1109/ISSCS.2017.8034899","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034899","url":null,"abstract":"This paper presents a 10-Gb/s power-efficient serial-link transceiver for the Internet-of-Everything applications. The proposed transceiver employs several techniques to reduce the power consumption. This includes the use of forward clocking with a simplified clock recovery scheme, multiplexing the transmitted signal at the output of voltage-mode drivers, and using modified slicers in the receiver side. The proposed transceiver is implemented using a 130-nm CMOS technology. It can transmit and receive 10-Gb/s serial data while employing a 5-GHz forwarded clock. The transceiver consumes 17.5 mA from a 1.2-V supply achieving a power efficiency of 2.2 pJ/bit.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126543826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A review and ultimate solution for output filters for high-power low-voltage DC/DC converters 大功率低压DC/DC变换器输出滤波器的综述和最终解决方案
2017 International Symposium on Signals, Circuits and Systems (ISSCS) Pub Date : 2017-07-01 DOI: 10.1109/ISSCS.2017.8034882
D. Neacşu, Dan Butnicu
{"title":"A review and ultimate solution for output filters for high-power low-voltage DC/DC converters","authors":"D. Neacşu, Dan Butnicu","doi":"10.1109/ISSCS.2017.8034882","DOIUrl":"https://doi.org/10.1109/ISSCS.2017.8034882","url":null,"abstract":"This paper revisits the selection of passive components for converters able to supply computer or telecom systems operated with 0.9 to 1.8V at 100s of Amps. Component selection is done from the available technology perspective rather than computation. Several low-cost (active or passive) improvements are suggested. Design is followed up with an example.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124478813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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