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2009 14th IEEE European Test Symposium最新文献

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A Two Phase Approach for Minimal Diagnostic Test Set Generation 最小诊断测试集生成的两阶段方法
2009 14th IEEE European Test Symposium Pub Date : 2009-05-25 DOI: 10.1109/ETS.2009.33
M. A. Shukoor, V. Agrawal
{"title":"A Two Phase Approach for Minimal Diagnostic Test Set Generation","authors":"M. A. Shukoor, V. Agrawal","doi":"10.1109/ETS.2009.33","DOIUrl":"https://doi.org/10.1109/ETS.2009.33","url":null,"abstract":"We optimize the full-response diagnostic fault dictionary from a given test set. The smallest set of vectors is selected without loss of diagnostic resolution of the given test set. We give an integer linear program (ILP) formulation using a fault diagnostic table. The complexity of the ILP is made manageable by two innovations. First, we define generalized fault independence. This property identifies many fault pairs that are guaranteed to be distinguished, significantly reducing the number of ILP constraints. Second, we propose a two-phase ILP approach. An initial phase, which uses existing procedures, selects a minimal detection test set. In a final phase, additional tests are then selected for the undiagnosed faults using a new diagnostic ILP. The overall minimized test set may be only slightly longer than that obtained from a one-step ILP optimization, but has advantages of significantly reduced computation complexity and reduced test time. Benchmark results show potential for very small diagnostic test sets.","PeriodicalId":329908,"journal":{"name":"2009 14th IEEE European Test Symposium","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114966160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits 一种检测数字电路中IDDQ缺陷的电压型测试方法
2009 14th IEEE European Test Symposium Pub Date : 2009-05-25 DOI: 10.1109/ETS.2009.34
J. Rius, Luis Elvira Villagra, M. Meijer
{"title":"A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits","authors":"J. Rius, Luis Elvira Villagra, M. Meijer","doi":"10.1109/ETS.2009.34","DOIUrl":"https://doi.org/10.1109/ETS.2009.34","url":null,"abstract":"A novel method to detect a defective IDDQ on top of highbackground current is proposed. Instead of the conventionalapproach that measures the quiescent current drawn by thecircuit-under-test (CUT), the proposed method is based on themeasurement of the voltage drop in a resistor spatially laid-outalong the CUT. Resistive shorts with a defective current of 2.14 mAon top of 83.11 mA of leakage current have been detected in a65nm CMOS test chip with controllable leakage. The proposedmethod also provides facilities to locate the defect in addition to detect it.","PeriodicalId":329908,"journal":{"name":"2009 14th IEEE European Test Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123394330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Partial Scan Approach for Secret Information Protection 保密信息保护的部分扫描方法
2009 14th IEEE European Test Symposium Pub Date : 2009-05-25 DOI: 10.1109/ETS.2009.15
M. Inoue, T. Yoneda, M. Hasegawa, H. Fujiwara
{"title":"Partial Scan Approach for Secret Information Protection","authors":"M. Inoue, T. Yoneda, M. Hasegawa, H. Fujiwara","doi":"10.1109/ETS.2009.15","DOIUrl":"https://doi.org/10.1109/ETS.2009.15","url":null,"abstract":"This paper proposes a secure scan design method whichprotects the circuits containing secret information such ascryptographic circuits from scan-based side channel attacks.The proposed method prevents the leakage of secretinformation by partial scan design based on a balancedstructure. We also guarantee the testability of both the designunder test and DFT circuitry, and therefore, realizeboth security and testability. Experiments for RSA circuitshows the effectiveness of the proposed method.","PeriodicalId":329908,"journal":{"name":"2009 14th IEEE European Test Symposium","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130658573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Novel Solution for the Built-in Gate Oxide Stress Test of LDMOS in Integrated Circuits for Automotive Applications 汽车集成电路中LDMOS内置栅氧化物应力测试的新解决方案
2009 14th IEEE European Test Symposium Pub Date : 2009-05-25 DOI: 10.1109/ETS.2009.18
V. Malandruccolo, M. Ciappa, W. Fichtner, H. Rothleitner
{"title":"Novel Solution for the Built-in Gate Oxide Stress Test of LDMOS in Integrated Circuits for Automotive Applications","authors":"V. Malandruccolo, M. Ciappa, W. Fichtner, H. Rothleitner","doi":"10.1109/ETS.2009.18","DOIUrl":"https://doi.org/10.1109/ETS.2009.18","url":null,"abstract":"Efficient screening procedures for the control of the gate oxide defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents a novel approach to the gate stress test of Lateral Diffused MOS transistors based on an embedded circuitry that includes logic control, high voltage generation, and leakage current monitoring. The concept, advantages and the circuit for the proposed built-in gate stress test procedure are described in very detail and illustrated by circuit simulation.","PeriodicalId":329908,"journal":{"name":"2009 14th IEEE European Test Symposium","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121201736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Test Encoding for Extreme Response Compaction 极限响应压缩的测试编码
2009 14th IEEE European Test Symposium Pub Date : 2009-05-25 DOI: 10.1109/ETS.2009.22
M. Kochte, S. Holst, Melanie Elm, H. Wunderlich
{"title":"Test Encoding for Extreme Response Compaction","authors":"M. Kochte, S. Holst, Melanie Elm, H. Wunderlich","doi":"10.1109/ETS.2009.22","DOIUrl":"https://doi.org/10.1109/ETS.2009.22","url":null,"abstract":"Optimizing bandwidth by compression and compaction always has to solve the trade-off between input bandwidth reduction and output bandwidth reduction. Recently it has been shown that splitting scan chains into shorter segments and compacting the shift data outputs into a singleparity bit reduces the test response data to one bit per cycle without affecting fault coverage and diagnostic resolution if the compactor's structure is included into the ATPG process.This test data reduction at the output side comes with challenges at the input side. The bandwidth requirement grows due to the increased number of chains and due to a drastically decreased amount of don't care values in the test patterns. The paper at hand presents a new iterative approach to test set encoding which optimizes bandwidth on both input and output side while keeping the diagnostic resolution and fault coverage. Experiments with industrial designs demonstrate that test application time, test data volume and diagnostic resolution are improved at the same time and for most designs testing with a bandwidth of three bits per cycle is possible.","PeriodicalId":329908,"journal":{"name":"2009 14th IEEE European Test Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114520222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Doubling Test Cell Throughput by On-Loadboard Hardware- Implementation and Experience in a Production Environment 通过板载硬件使测试单元吞吐量加倍-在生产环境中的实现和经验
2009 14th IEEE European Test Symposium Pub Date : 2009-05-25 DOI: 10.1109/ETS.2009.38
Frank-Uwe Faber, Matthias Beck, M. Rudack, Olivier Barondeau, Thomas Rabenalt, M. Gössel, A. Leininger
{"title":"Doubling Test Cell Throughput by On-Loadboard Hardware- Implementation and Experience in a Production Environment","authors":"Frank-Uwe Faber, Matthias Beck, M. Rudack, Olivier Barondeau, Thomas Rabenalt, M. Gössel, A. Leininger","doi":"10.1109/ETS.2009.38","DOIUrl":"https://doi.org/10.1109/ETS.2009.38","url":null,"abstract":"This paper reports the experience being made during the implementation of low pin count techniques and their insertion into a production environment. The techniques applied are \"on-loadboard compare\" and \"shared driver\". Already known on a concept level for an on-chip approach, in this paper the transfer to an on-loadboard solution is presented. Emphasis is put on production related aspects. Practical experience, challenges, and pitfalls are described to allow a better assessment of risks and benefits of the investigated methods.","PeriodicalId":329908,"journal":{"name":"2009 14th IEEE European Test Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115478732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Automatic Functional Stress Pattern Generation for SoC Reliability Characterization 自动功能应力模式生成SoC可靠性表征
2009 14th IEEE European Test Symposium Pub Date : 2009-05-25 DOI: 10.1109/ETS.2009.16
D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sánchez, M. Reorda
{"title":"Automatic Functional Stress Pattern Generation for SoC Reliability Characterization","authors":"D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sánchez, M. Reorda","doi":"10.1109/ETS.2009.16","DOIUrl":"https://doi.org/10.1109/ETS.2009.16","url":null,"abstract":"Reliability testing is increasingly used not only to reduce Infant Mortality effects, but also for Reliability Characterization. This paper first discusses the characteristics of the stimuli to be used during Reliability Characterization experiments, and outlines the importance of adopting a functional approach. Secondly, the paper describes a novel approach to automatically generate suitable stress patterns to be used during the Reliability characterization process of Systems-on-chip. The generation process uses an evolutionary algorithm driven by suitable state toggling-related metrics purposely defined in the paper.Costs and benefits of the proposed approach are highlighted, supported by the results gathered on a test vehicle released on a 90nm technology.","PeriodicalId":329908,"journal":{"name":"2009 14th IEEE European Test Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124115914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques 利用高效动态学习技术提高sat延迟测试生成的鲁棒性
2009 14th IEEE European Test Symposium Pub Date : 2009-05-25 DOI: 10.1109/ETS.2009.13
Stephan Eggersglüß, R. Drechsler
{"title":"Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques","authors":"Stephan Eggersglüß, R. Drechsler","doi":"10.1109/ETS.2009.13","DOIUrl":"https://doi.org/10.1109/ETS.2009.13","url":null,"abstract":"Due to the increased speed in modern designs, testing for delay faults has become an important issue in the post-production test of manufactured chips. A high fault coverage is needed to guarantee the correct temporal behavior. Today's ATPG algorithms have difficulties to reach the desired fault coverage due to the high complexity of modern designs. In this paper, we describe how to efficiently integrate the reuse of learned information into state-of-the-art SAT-based ATPG algorithms and, by this, reduce the number of unclassified faults significantly. For further reduction, a post-classification phase is presented. Experimental results for ATPG for delay faults on large industrial circuits show the robustness and feasibility of the approach.","PeriodicalId":329908,"journal":{"name":"2009 14th IEEE European Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128986323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Categorizing and Analysis of Activated Faults in the FlexRay Communication Controller Registers FlexRay通信控制器寄存器中激活故障的分类与分析
2009 14th IEEE European Test Symposium Pub Date : 2009-05-25 DOI: 10.1109/ets.2009.21
Yasser Sedaghat, S. Miremadi
{"title":"Categorizing and Analysis of Activated Faults in the FlexRay Communication Controller Registers","authors":"Yasser Sedaghat, S. Miremadi","doi":"10.1109/ets.2009.21","DOIUrl":"https://doi.org/10.1109/ets.2009.21","url":null,"abstract":"FlexRay communication protocol is expected becoming the de-facto standard for distributed safety-critical systems. In this paper, transient single bit-flip faults were injected into the FlexRay communication controller to categorize and analyze the activated faults. In this protocol, an activated fault results in one or more error types which are Boundary violation, Conflict, Content, Freeze, Synchronization, and Syntax. To study the activated faults, a FlexRay bus network, composed of four nodes, was modeled by Verilog HDL; and a total of 135,600 transient faults were injected in only one node, where 9,342 (6.9%) of the faults were activated. The results show that the Synchronization error is the widespread error with the occurrence ratio of about 70.1%. The Boundary violation and the Syntax errors have the occurrence ratios of 32.4% and 24.6%, respectively. The results also show that the Freeze error which more frequent resulted system failures has the occurrence ratio of about 17.3%.","PeriodicalId":329908,"journal":{"name":"2009 14th IEEE European Test Symposium","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121657876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Algorithms for ADC Multi-site Test with Digital Input Stimulus 基于数字输入刺激的ADC多点测试算法
2009 14th IEEE European Test Symposium Pub Date : 2009-05-25 DOI: 10.1109/ETS.2009.17
Xiaoqin Sheng, H. Kerkhoff, A. Zjajo, G. Gronthoud
{"title":"Algorithms for ADC Multi-site Test with Digital Input Stimulus","authors":"Xiaoqin Sheng, H. Kerkhoff, A. Zjajo, G. Gronthoud","doi":"10.1109/ETS.2009.17","DOIUrl":"https://doi.org/10.1109/ETS.2009.17","url":null,"abstract":"This paper reports two novel algorithms based on time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both algorithms, a pulse signal, in its slightly adapted form to allow sufficient time for converter settling, is taken as the test stimulus reliving the burden placed on accuracy requirement of excitation source. The objective of the test scheme is not to completely replace traditional specification-based tests, but to provide a reliable method for early identification of excessive parameter variations in production test that allows quickly discarding of most of the faulty circuits before going through the conventional test. The efficiency of the methods is validated on a 6-bit flash ADC.","PeriodicalId":329908,"journal":{"name":"2009 14th IEEE European Test Symposium","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116516830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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