{"title":"Implementing asynchronous embryonic circuits using AARDVArc","authors":"Alexander H. Jackson, A. Tyrrell","doi":"10.1109/EH.2002.1029889","DOIUrl":"https://doi.org/10.1109/EH.2002.1029889","url":null,"abstract":"Embryonic arrays display the desirable biological characteristics of fault-tolerance and a complex structure. They do not generally make use of a further biological characteristic; fundamentally asynchronous operation. Further to the inherent advantages of an asynchronous approach, scalability and reliability are perceived as benefits pertinent to embryonic designs. This paper advances a simulated asynchronous embryonic design by realising its functional logic using a Xilinx Virtex FPGA. The AARDVArc program augments the standard design tools to achieve this macromodule based implementation. The design is compared to a similar synchronous design in terms of its logic requirement and performance. Although requiring additional resources and operating less quickly than its synchronous counterpart, this work forms the basis for a fully asynchronous practical embryonic array.","PeriodicalId":322028,"journal":{"name":"Proceedings 2002 NASA/DoD Conference on Evolvable Hardware","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131964460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Physical support for evolution in reconfigurable devices","authors":"P. Athanas","doi":"10.1109/EH.2002.1029859","DOIUrl":"https://doi.org/10.1109/EH.2002.1029859","url":null,"abstract":"Summary form only given. In recent years, there have been several architectures introduced specifically with hardware evolution in mind. In addition to these devices, many research and commercial chips have emerged that, while not specifically designed for evolution nor even considered as evolvable hardware, possess the properties considered essential for evolvable systems. There are a minimum set of properties that must be supported required for hardware evolution to occur in an autonomous embedded environment. A device deemed evolvable typically supports one or more of the following properties: (i) having an architecture that is flexible and conducive to a wide variety of solutions in a given problem domain, (ii) having the ability to assess its own behavior and compare it with a standard, (iii) having the ability to deduce circuit modifications, and (iv) having the architectural support to modify the functionality of the hardware (on-line). This talk will explore contemporary commodity and research-grade single-chip devices that were not designed with evolution in mind, yet provide, at minimum, the foundation for evolution. Illustrative examples will be given when possible.","PeriodicalId":322028,"journal":{"name":"Proceedings 2002 NASA/DoD Conference on Evolvable Hardware","volume":"268 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116499284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evolving quantum circuits using genetic algorithm","authors":"M. Lukac, M. Perkowski","doi":"10.1109/EH.2002.1029883","DOIUrl":"https://doi.org/10.1109/EH.2002.1029883","url":null,"abstract":"In this paper we focus on a general approach of using genetic algorithm (GA) to evolve Quantum circuits (QC). We propose a generic GA to evolve arbitrary quantum. circuit specified by a (target) unitary matrix as well as a specific encoding that reduces the time of calculating the resultant unitary matrices of chromosomes. We demonstrate that, in contrast to previous approaches, our encoding allows synthesis of small quantum circuits of arbitrary type, using standard genetic operators.","PeriodicalId":322028,"journal":{"name":"Proceedings 2002 NASA/DoD Conference on Evolvable Hardware","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125906206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Chromosome representation through adjacency matrix in evolutionary circuits synthesis","authors":"A. C. M. Filho, Fabio A. Salazar, P. P. Canazio","doi":"10.1109/EH.2002.1029872","DOIUrl":"https://doi.org/10.1109/EH.2002.1029872","url":null,"abstract":"The use of adjacency matrices to the chromosome coding in evolutionary circuits techniques is proposed. The approach is shown to overcome some of the drawbacks associated with other coding schemes simplifying the implementation of the evolution process. It is particularly shown that the proposed coding scheme reduces considerably the generation of anomalous circuits increasing the efficiency of the overall process. Other important issues such as fault tolerance, sensitivity and robustness of the synthesized circuits are addressed.","PeriodicalId":322028,"journal":{"name":"Proceedings 2002 NASA/DoD Conference on Evolvable Hardware","volume":"438 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133662499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"How to evolve safe control strategies","authors":"G. Greenwood, X. Song","doi":"10.1109/EH.2002.1029876","DOIUrl":"https://doi.org/10.1109/EH.2002.1029876","url":null,"abstract":"Autonomous space vehicles need adaptive control strategies that can accommodate unanticipated environmental conditions. The evaluation of new strategies can often be done only by actually trying them out in the real physical environment. Consequently, a candidate control strategy must be deemed safe - i.e., it won't damage any systems - prior to being tested online. How to do this efficiently has been a challenging problem. We propose using evolutionary programming in conjunction with a formal verification technique (called model checking) to evolve candidate control strategies that are guaranteed to be safe for implementation and evaluation.","PeriodicalId":322028,"journal":{"name":"Proceedings 2002 NASA/DoD Conference on Evolvable Hardware","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127654364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An immunochip architecture and its emulation","authors":"A. Tarakanov, D. Dasgupta","doi":"10.1109/EH.2002.1029892","DOIUrl":"https://doi.org/10.1109/EH.2002.1029892","url":null,"abstract":"The paper proposes an architecture for building immunochips and provides a mathematical framework in describing some of its operations using the concepts of proteins and immune networks. This approach is considered as the computational basis of an \"immunochip\", and this paper describes its implementation procedure. The proposed immunochip is emulated in software and evaluated with the problem of detecting of dangerous ballistic situations in near-Earth space.","PeriodicalId":322028,"journal":{"name":"Proceedings 2002 NASA/DoD Conference on Evolvable Hardware","volume":"3 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129704385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Circuit morphologies and ontogenies","authors":"R. T. Edwards","doi":"10.1109/EH.2002.1029891","DOIUrl":"https://doi.org/10.1109/EH.2002.1029891","url":null,"abstract":"Evolvable hardware circuits and algorithms rarely take inspiration from biology beyond the idea of the genetic algorithm. I have applied key concepts of self-organization and complexity theory (primarily Stuart Kauffman's \"auto-catalytic sets\") to the problem of circuit ontogeny, in which a genotype becomes a phenotype through a process of growth rather than a direct mapping. I present two novel hardware architectures, one analog and one digital, as well as a biologically-inspired method of encoding the genome of a circuit, and processes for circuit growth. Among the findings are the remarkable result that \"adult-hood\" is simply a stable basin of attraction reached by iterating the (nonlinear) growth process, and that the same process continued past circuit maturity implements a form of fault-tolerance.","PeriodicalId":322028,"journal":{"name":"Proceedings 2002 NASA/DoD Conference on Evolvable Hardware","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128547197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The implementation of an evolvable hardware system for Real Time Image Registration on a System-on-Chip platform","authors":"J. Evans, T. Arslan","doi":"10.1109/EH.2002.1029878","DOIUrl":"https://doi.org/10.1109/EH.2002.1029878","url":null,"abstract":"This paper presents an evolvable hardware system for real time image registration implemented on a conventional system-on-chip platform. In order to provide flexibility most components of the genetic algorithm, which forms the basis of the evolvable hardware, are implemented as embedded software and ported to various components on the system-on-chip platform. The paper describes optimisation techniques in order to achieve real time speed for porting the algorithm on an ARM7 based system-on-chip platform. Results for the execution on the host platform and the system-on-chip target are presented. Through analysis of the results, a modified platform is proposed for the implementation of the evolvable hardware system. This enhanced system architecture includes a high performance digital signal processing intellectual property core.","PeriodicalId":322028,"journal":{"name":"Proceedings 2002 NASA/DoD Conference on Evolvable Hardware","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134027590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"\"TiPo\" - a \"Timed pointer\" neural net model with superior evolvabilities for implementation in a second-generation brain-building machine BM2","authors":"J. Dinerstein, H. D. Garis","doi":"10.1109/EH.2002.1029895","DOIUrl":"https://doi.org/10.1109/EH.2002.1029895","url":null,"abstract":"This paper introduces TiPo, a new neural net model with superior evolvabilities. TiPo neural nets can dynamically change their structure with each clock tick. This provides enhanced computability for highly dynamic functions, such as curve following. Curve following is valuable for applications such as robot motion control.","PeriodicalId":322028,"journal":{"name":"Proceedings 2002 NASA/DoD Conference on Evolvable Hardware","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127680690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Towards evolvable analog fuzzy logic controllers","authors":"J.L.M. do Amaral, J.L.M. do Amaral","doi":"10.1109/EH.2002.1029874","DOIUrl":"https://doi.org/10.1109/EH.2002.1029874","url":null,"abstract":"Fuzzy logic has proved to be a very powerful technique in the discipline of system control. A fuzzy logic controller is defined by a collection of fuzzy if-then rules and a set of membership functions characterizing the linguistic terms associated with the inputs and output of the fuzzy controller. This paper discusses the use of an evolvable hardware (EHW) platform in the synthesis of analog electronic circuits for fuzzy logic controllers. The EHW analog platform is a field programmable analog array (FPAA). FPAAs constitute the state of the art in the technology of reconfigurable platforms. These devices will become the building blocks of a forthcoming class of hardware, with the important features of self-adaptation and self-repairing, through automatic reconfiguration. Automatic reconfiguration of FPAAs has be driven by evolutionary computation techniques such as genetic algorithms. In this article we propose the implementation of fuzzy logic controllers, based on building blocks, developed on an FPAA, and present an intrinsic evolution example of a building block: a simple membership function.","PeriodicalId":322028,"journal":{"name":"Proceedings 2002 NASA/DoD Conference on Evolvable Hardware","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130222669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}