2009 NASA/ESA Conference on Adaptive Hardware and Systems最新文献_第3页

Self-Testable and Self-Repairable Bio-Inspired Configurable Circuits 自我测试和自我修复的仿生可配置电路

2009 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.19

A. Stauffer, J. Rossier

引用次数: 8

Implementation of Highly Pipelined Datapaths on a Reconfigurable Asynchronous Substrate 在可重构异步基板上实现高度流水线化的数据路径

2009 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.56

Khodor Ahmad Fawaz, T. Arslan, Iain A. B. Lindsay

{"title":"Implementation of Highly Pipelined Datapaths on a Reconfigurable Asynchronous Substrate","authors":"Khodor Ahmad Fawaz, T. Arslan, Iain A. B. Lindsay","doi":"10.1109/AHS.2009.56","DOIUrl":"https://doi.org/10.1109/AHS.2009.56","url":null,"abstract":"In programmable logic devices, the timing requirements change depending on what datapath is being mapped and the level of pipelining required. The added flexibility of such architectures translates to complexity in the design of their clocking scheme, both on the silicon and software level. Using asynchronous techniques to design the programmable elements and interconnects simplifies this problem by replacing the global clock signal with local handshaking. In asynchronous programmable devices, the handshaking protocol implements communication and synchronisation among the components of any mapped datapath irrespective of its length. This paper describes the design of an asynchronous substrate for implementing highly pipelined datapaths. A novel technique for conditional acknowledge synchronisation was used in the interconnect design. Two asynchronous arrays of coarse-grain adders and multipliers were built and compared with an equivalent clocked architecture. For a sample FFT, our asynchronous designs showed a reduction of up to 10% in energy consumption and 4.5% in area, which came at a cost of a 2.5% reduction in throughput over the equivalent synchronous implementation.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127988848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Comparison of the Uniform and Non-Uniform Cellular Automata-Based Approach to the Development of Combinational Circuits 基于均匀和非均匀元胞自动机的组合电路开发方法的比较

2009 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.42

Michal Bidlo, Z. Vašíček

{"title":"Comparison of the Uniform and Non-Uniform Cellular Automata-Based Approach to the Development of Combinational Circuits","authors":"Michal Bidlo, Z. Vašíček","doi":"10.1109/AHS.2009.42","DOIUrl":"https://doi.org/10.1109/AHS.2009.42","url":null,"abstract":"Cellular automata-based model has been shown as a useful developmental model in the evolutionary design of digital circuits at the gate level. Uniform one-dimensional cellular automata have been successfully applied to the circuit design task so far. Moreover, the initial experiments performed during our previous research have demonstrated the possibility of applying non-uniform cellular automata to the circuits design which is the main objective of the proposed paper. We will investigate this approach considering several classes of combinational circuits, provide an analysis of the obtained results and their comparison with the results of the uniform cellular automata-based model. It will be shown that evolution is able to find (in general a different) local transition function for each cell of the automaton according to which the target circuit is developed. Two different case studies will be presented in order to demonstrate the abilities of the proposed method. The first case study deals with the development of combinational multipliers and the second one is intended to develop combinational dividers. The obtained experimental results will be compared to our previous approach in which uniform cellular automata were applied. The proposed non-uniform approach enables to design circuits that we were not able to develop successfully using the uniform cellular automata.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123259837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Evolution of Impulse Bursts Noise Filters 脉冲突发噪声滤波器的发展

2009 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.33

Z. Vašíček, Michal Bidlo, L. Sekanina, J. Tørresen, K. Glette, M. Furuholmen

引用次数: 10

Nominal-Yield-Area Tradeoff in Automatic Synthesis of Analog Circuits: A Genetic Programming Approach Using Immune-Inspired Operators 模拟电路自动合成中的名义产出面积权衡:一种使用免疫激励算子的遗传规划方法

2009 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.32

P. Conca, Giuseppe Nicosia, Giovanni Stracquadanio, J. Timmis

{"title":"Nominal-Yield-Area Tradeoff in Automatic Synthesis of Analog Circuits: A Genetic Programming Approach Using Immune-Inspired Operators","authors":"P. Conca, Giuseppe Nicosia, Giovanni Stracquadanio, J. Timmis","doi":"10.1109/AHS.2009.32","DOIUrl":"https://doi.org/10.1109/AHS.2009.32","url":null,"abstract":"The synthesis of analog circuits is a complex and expensive task; whilst there are various approaches for the synthesis of digital circuits, analog design is intrinsically more difficult since analog circuits process voltages in a continuous range. In the field of analog circuit design, the genetic programming approach has received great attention, affording the possibility to design and optimize a circuit at the same time. However, these algorithms have limited industrial relevance, since they work with ideal components. Starting from the well known results of Koza and co-authors, we introduce a new evolutionary algorithm, called elitist Immune Programming (EIP), that is able to synthesize an analog circuit using industrial components series in order to produce reliable and low cost circuits. The algorithm has been used for the synthesis of low-pass filters; the results were compared with the genetic programming, and the analysis shows that EIP is able to design better circuits in terms of frequency response and number of components. In addition we conduct a complete yield analysis of the discovered circuits, and discover that EIP circuits attain a higher yield than the circuits generated via a genetic programming approach, and, in particular, the algorithm discovers a Pareto Front which respects nominal performance (sizing), number of components (area) and yield (robustness).","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121029905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Implementation of an IEEE802.11a Transmitter Module for a Reconfigurable System-on-a-Chip Design 用于可重构片上系统设计的IEEE802.11a发送模块的实现

2009 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.61

T. Vladimirova, J. Paul

引用次数: 6

Self-Scaling Stream Processing: A Bio-Inspired Approach to Resource Allocation through Dynamic Task Replication 自扩展流处理:通过动态任务复制实现资源分配的仿生方法

2009 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.25

Pierre-André Mudry, G. Tempesti

引用次数: 6

Effect of a Central Antenna Element on the Directivity, Half-Power Beamwidth and Side-Lobe Level of Circular Antenna Arrays 中心天线单元对圆形天线阵列方向性、半功率波束宽度和旁瓣电平的影响

2009 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.63

Virgilio Zúñiga, N. Haridas, A. Erdogan, T. Arslan

引用次数: 10

Mersenne Twister Random Number Generation on FPGA, CPU and GPU 基于FPGA、CPU和GPU的梅森扭扭随机数生成

2009 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.11

Xiang Tian, K. Benkrid

{"title":"Mersenne Twister Random Number Generation on FPGA, CPU and GPU","authors":"Xiang Tian, K. Benkrid","doi":"10.1109/AHS.2009.11","DOIUrl":"https://doi.org/10.1109/AHS.2009.11","url":null,"abstract":"Random number generation is a very important operation in computational science e.g. in Monte Carlo simulations methods. It is also a computationally intensive operation especially for high quality random number generation. In this paper, we present the design and implementation of a parallel implementation of one of the most widely used random number generators, namely the Mersenne Twister. The latter is very widely used in high performance computing applications such as financial computing. Implementations of our parallel Mersenne Twister number generator core on Xilinx Virtex4 FPGAs achieve a throughput of 26.13 billion random samples per second. The paper also reports equivalent parallel software implementations running on an Intel Core 2 Quad Q9300 CPU with 8 GB RAM, using multi-threading technology and the Intel® Math Kernel Library (MKL), as well as on an NVIDIA 8800 GTX GPU. Comparative results show that our FPGA-based implementation outperforms equivalent CPU and GPU implementations by ~25x and ~9x respectively. Moreover, when using the same amount of energy, the FPGA can generate 37x and 35x more Mersenne Twister random samples than the CPU and the GPU, respectively.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129310939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 54

Adapting a Genotype-phenotype Mapping to Phenotypic Complexity 适应基因型-表型定位的表型复杂性

2009 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2009-07-29 DOI: 10.1109/AHS.2009.47

Morten Hartmann, Tim Goedeweeck

引用次数: 1