Implementation of Highly Pipelined Datapaths on a Reconfigurable Asynchronous Substrate

Abstract

In programmable logic devices, the timing requirements change depending on what datapath is being mapped and the level of pipelining required. The added flexibility of such architectures translates to complexity in the design of their clocking scheme, both on the silicon and software level. Using asynchronous techniques to design the programmable elements and interconnects simplifies this problem by replacing the global clock signal with local handshaking. In asynchronous programmable devices, the handshaking protocol implements communication and synchronisation among the components of any mapped datapath irrespective of its length. This paper describes the design of an asynchronous substrate for implementing highly pipelined datapaths. A novel technique for conditional acknowledge synchronisation was used in the interconnect design. Two asynchronous arrays of coarse-grain adders and multipliers were built and compared with an equivalent clocked architecture. For a sample FFT, our asynchronous designs showed a reduction of up to 10% in energy consumption and 4.5% in area, which came at a cost of a 2.5% reduction in throughput over the equivalent synchronous implementation.