{"title":"A Data Caching Approach for Sensor Applications","authors":"Khaled Almiani, J. Taheri, Anastasios Viglas","doi":"10.1109/PDCAT.2009.57","DOIUrl":"https://doi.org/10.1109/PDCAT.2009.57","url":null,"abstract":"In sensor network applications, data gathering mechanisms, which are based on multi-hop forwarding, can be expensive in terms of energy. This limitation challenges the use of sensor networks for applications that demand a predefined operational-lifetime. To avoid this problem, using of Mobile Element (ME) as a mechanical data carrier has emerged as a promising approach. However, practical considerations such as the ME speed and route planning, sensor buffer size and data frequency generation constraints impose limits on this approach. To address these issues, we propose a natural hybrid approach that combines two approaches of ME and multi-hop forwarding. We consider the problem of determining the path of the ME, in which the length of this path is bounded by pre-determined length. This path will visit a subset of the nodes. These selected nodes will work as caching points and will aggregate the other nodes’ data. The caching point nodes are selected with the aim of reducing the energy expenditures due to multi-hop forwarding. To address this problem, we present a heuristic-based solution and compare its performance against the optimal solution. We obtain the optimal solution by providing an Integer Linear Program for this problem.","PeriodicalId":312929,"journal":{"name":"2009 International Conference on Parallel and Distributed Computing, Applications and Technologies","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128250716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Idiom Recognition and Program Scheme Recognition Based Program Transformations for Performance Tuning--Beyond Compiler Optimizations--","authors":"S. Hiroyuki","doi":"10.1109/PDCAT.2009.66","DOIUrl":"https://doi.org/10.1109/PDCAT.2009.66","url":null,"abstract":"Much effort has been performed for performance tuning. However, it is becoming clear that performance tuning is much harder in complicated modern parallel architectures. For performance tuning, compiler approach was prevailing in the era of vector architecture. Today, instead, PSE approach which provides users with abstract programming emerges, which also has a problem in tuning fine points. Another approach is “ autotuning” which is a brute force attack for performance tuning. We have proposed that idiom recognition can be a bridge between abstract source programs and concrete architectures. This paper applies term rewriting theory -a very general framework to the idiom recognition system. Moreover, we apply higher order term rewriting to find better patterns. We show that tiling and recursive algorithm scheme patterns can be reinvented by the extended idiom recognition. Furthermore, we discuss a method of enrichment of candidates of optimizations by using the general framework of graph rewriting.","PeriodicalId":312929,"journal":{"name":"2009 International Conference on Parallel and Distributed Computing, Applications and Technologies","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130053450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Simple Parallel Convex Hulls Algorithm for Sorted Points and the Performance Evaluation on the Multicore Processors","authors":"Masaya Nakagawa, Duhu Man, Yasuaki Ito, K. Nakano","doi":"10.1109/PDCAT.2009.56","DOIUrl":"https://doi.org/10.1109/PDCAT.2009.56","url":null,"abstract":"Finding a vast array of applications, the problem of computing the convex hull of a set of sorted points in the plane is one of the fundamental tasks in pattern recognition, morphology and image processing. The main contribution of this paper is to show a simple parallel algorithm for computing the convex hull of a set of n sorted points in the plane and evaluate the performance on the dual quad-core processors. The experimental results show that, our implementation achieves a speed-up factor of approximately 7 using 8 processors. Since the speed-up factor of more than 8 is not possible, our parallel implementation for computing the convex hull is close to optimal. Also, for 2 or 4 processors, we achieved a super linear speed up.","PeriodicalId":312929,"journal":{"name":"2009 International Conference on Parallel and Distributed Computing, Applications and Technologies","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132155905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Lambda-Systolic Routing in a Wavelength-Division Multiplexed All-Optical Butterfly","authors":"Risto T. Honkanen","doi":"10.1109/PDCAT.2009.21","DOIUrl":"https://doi.org/10.1109/PDCAT.2009.21","url":null,"abstract":"In this paper we present an all-optical network architecture and a routing protocol for it. A 2r-dimensional coloured optical butterfly (COBF) network consists of P = $2^{2r}$ processors, N = $r2^{2r+1}$ routing nodes, and E = $r2^{2r+2}$ edges. The routing machinery is divided in an r-dimensional front-end and 2r = $sqrt{P}$ r-dimensional back-ends. Processors are deployed at the level 0 (identical to level 2r) nodes of the network. Routing is based on the use of $sqrt{P}$ wavelength-multiplexed optical signals, a cyclic control bit sequence, and scheduled sendings of packets. The routing protocol ensures that no electro-optical conversion is needed in the intermediate routing nodes and all the packets injected into the routing machinery will reach their target without collisions. We then present an analysis of the routing algorithm with a batch type routing problem. According to our experiments, a work-optimal routing of an h-relation is achieved with a reasonable size of h ÎΩ(P).","PeriodicalId":312929,"journal":{"name":"2009 International Conference on Parallel and Distributed Computing, Applications and Technologies","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131357586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Error Compensation for Cricket Indoor Location System","authors":"Shu-De Zhou, Haoran Feng, Ruixi Yuan","doi":"10.1109/PDCAT.2009.54","DOIUrl":"https://doi.org/10.1109/PDCAT.2009.54","url":null,"abstract":"Cricket is a fine-grained indoor location system utilizing beacons transmitting both ultrasound and radio wave signals. However, the system accuracy is greatly impacted by the relative angle and distance between the beacon and listener. This paper proposes a low cost method to improve the system precision by means of incremental error compensation. The ultrasonic detecting error, which directly affects the accuracy of time-difference-of-arrival (TDOA), is first analyzed and verified via experiments. Then an error compensation method is designed based on total least squares (TLS) to further improve the Cricket’s localization performance. Experimental results show that the average error of localization is reduced to 5.60cm with compensation, compared with 9.06cm of the original Cricket method. The standard deviation of the errors is reduced from 7.80cm to 3.99cm. This method lays a foundation for further improving the existing ultrasound-related distance measurement method.","PeriodicalId":312929,"journal":{"name":"2009 International Conference on Parallel and Distributed Computing, Applications and Technologies","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123274995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fabienne Carrier, Stéphane Devismes, F. Petit, Yvan Rivierre
{"title":"Space-Optimal Deterministic Rendezvous","authors":"Fabienne Carrier, Stéphane Devismes, F. Petit, Yvan Rivierre","doi":"10.1109/PDCAT.2009.13","DOIUrl":"https://doi.org/10.1109/PDCAT.2009.13","url":null,"abstract":"In this paper, we address the deterministic rendezvous of mobile agents into any unoriented connected graph. The agents are autonomous, oblivious, move asynchronously. For this problem, we exhibit some time and space lower bounds as well as some necessary conditions. We also propose an algorithm that is space-optimal and asymptotically optimal in rounds.","PeriodicalId":312929,"journal":{"name":"2009 International Conference on Parallel and Distributed Computing, Applications and Technologies","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122965129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Task Selection Based Power-aware Scheduling Algorithm for Applying DVS","authors":"Yuichiro Mori, K. Asakura, Toyohide Watanabe","doi":"10.1109/PDCAT.2009.36","DOIUrl":"https://doi.org/10.1109/PDCAT.2009.36","url":null,"abstract":"Recently, power consumption of server computers is one of the most important topics. Although DVS (Dynamic Voltage Scaling) can reduce power consumption, this method is only used at idle time or low load computation time, generally. In this paper, we propose a task scheduling algorithm for reducing power consumption especially at high load computation time. DVS is applied to tasks that are not in critical path, which can reduce more power consumption by introducing a task selection mechanism without increasing the makespan of task graphs. Experimental results show that our algorithm can reduce about 9.1% and 12.8% of power consumption on 4 and 8 processors respectively on average in comparison with the existing method.","PeriodicalId":312929,"journal":{"name":"2009 International Conference on Parallel and Distributed Computing, Applications and Technologies","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115308996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Study of an Infrastructure for Research and Development of Many-Core Processors","authors":"Koh Uehara, Shimpei Sato, T. Miyoshi, Kenji Kise","doi":"10.1109/PDCAT.2009.77","DOIUrl":"https://doi.org/10.1109/PDCAT.2009.77","url":null,"abstract":"Many-core processors which have thousands of cores on a chip will be realized. We developed an infrastructure which accelerates the research and development of such many-core processors. This paper describes three main elements provided by our infrastructure. The first element is the definition of simple many-core processor architecture called M-Core. The second is SimMc, a software simulator of M-Core. The third is the software library MClib which helps the development of application programs for M-Core. The simulation speed of SimMc and the parallelization efficiency of M-Core are evaluated using some benchmark programs. We show that our infrastructure accelerates the research and development of many-core processors.","PeriodicalId":312929,"journal":{"name":"2009 International Conference on Parallel and Distributed Computing, Applications and Technologies","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121183749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Bellavia, M. Cipolla, D. Tegolo, Cesare Valenti
{"title":"An Evolution of the Non-Parameter Harris Affine Corner Detector: A Distributed Approach","authors":"F. Bellavia, M. Cipolla, D. Tegolo, Cesare Valenti","doi":"10.1109/PDCAT.2009.45","DOIUrl":"https://doi.org/10.1109/PDCAT.2009.45","url":null,"abstract":"A parallel version of a new automatic Harris-based corner detector is presented. A scheduler to dynamically and homogeneously distribute high computational workload on heterogeneous parallel architectures such as Grid systems has been implemented to speedup the whole procedure. Experimental results show the robustness of the underlying scheduler, which can be easily exploited in various automatic image analysis systems.","PeriodicalId":312929,"journal":{"name":"2009 International Conference on Parallel and Distributed Computing, Applications and Technologies","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122511219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Building Highly Available Cluster File System Based on Replication","authors":"Liang Cao, Yu Wang, Jin Xiong","doi":"10.1109/PDCAT.2009.14","DOIUrl":"https://doi.org/10.1109/PDCAT.2009.14","url":null,"abstract":"In order to gain better cost-effectiveness, current large-scale storage systems are typically built up by thousands of individual components. As systems scale up, the probability of the failure of multiple components increases. And for large-scale storage system, failures are normal rather than exception. How to build file systems providing both high throughput and highly available service under such circumstances is a big challenge. We have designed and implemented HA-DCFS3, a highly available cluster file system prototype. It uses a scalable replication algorithm called Asynchronous Primary Copy Protocol (APCP). Unlike traditional Primary Copy Protocol that must synchronize updates to all replicas, APCP introduces an asynchronous approach where write operation is permitted to be synchronized to a subset of replicas. This flexible approach greatly improves the write performance. Furthermore, HA-DCFS3 also introduces a fine-grained failure detection called “ data path detection”, which is integrated into the fault-tolerant framework based on data replication. Hence, HA-DCFS3 can provide continuous service even when component failures occur. And finally, HA-DCFS3 adopts a two-level data recovery strategy that handles transient failures with reintegration and persistent failures with re-replication respectively to reduce the cost of data repair. Our performance results show that HA-DCFS3 can deliver high and scalable aggregate performance and provide highly available service at very low cost.","PeriodicalId":312929,"journal":{"name":"2009 International Conference on Parallel and Distributed Computing, Applications and Technologies","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124947896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}