Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies最新文献

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Design of a hybrid digital-analog neural co-processor for signal processing 一种用于信号处理的混合数模神经协处理器的设计
A. Romariz, P. Ferreira, J. Campêlo, M. L. Graciano, J. C. Costa
{"title":"Design of a hybrid digital-analog neural co-processor for signal processing","authors":"A. Romariz, P. Ferreira, J. Campêlo, M. L. Graciano, J. C. Costa","doi":"10.1109/EURMIC.1996.546477","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546477","url":null,"abstract":"A hybrid architecture for neural coprocessing is presented. A fixed set of analog multipliers and capacitors (analog memory) emulates multilayer perceptrons through digitally-controlled multiplexing. Thus parallelism is partially preserved without direct analog implementation of the whole structure. Details of system VLSI implementation are given, along with simulation results and performance estimation.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121653088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Implementation of processor cells for array algorithms on FPGAs 阵列算法处理器单元在fpga上的实现
István Vassányi, István Erényi
{"title":"Implementation of processor cells for array algorithms on FPGAs","authors":"István Vassányi, István Erényi","doi":"10.1109/EURMIC.1996.546364","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546364","url":null,"abstract":"Recent advances in FPGA technology offer a suitable environment for massively parallel, fine-grain array architectures. The paper gives geometric criteria for an optimal \"jigsaw tessellated\" processor cell, and cost function for cell placement. The paper demonstrates the use of FPGA-based processor arrays by the implementation results of two cellular image processing algorithms. The outlined concepts are being implemented in a placement-routing tool.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127144979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Transparency in a replicated network file system 复制网络文件系统的透明度
C. Chin, S. Tsai
{"title":"Transparency in a replicated network file system","authors":"C. Chin, S. Tsai","doi":"10.1109/EURMIC.1996.546393","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546393","url":null,"abstract":"File servers acting as centralized data sharing and storage stations are very crucial in modern network environments. Failure and inefficiency of a file server would be unacceptable and thus data replication is necessary to provide fault-tolerant and high-performance services. In this article, we present a replicated network file service that follows the Sun NFS protocol. Replication transparency and failure transparency are emphasized in the design. Any NFS client implemented on existing systems can use our fault-tolerant service without any modifications. In the current prototype, the simple primary-backup model is used to ensure data consistency between servers. Two distributed algorithms were designed to monitor and maintain the server modes. Performance analysis shows that the prototype system is sufficient to support a mostly-read environment, and it is possible that a high-performance file service can be accomplish in future developments.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125238515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Behaviour-preserving transformations in SHE: a formal approach to architecture design SHE中的行为保持转换:架构设计的正式方法
J. Voeten, P.H.A. van der Putten, M. Stevens
{"title":"Behaviour-preserving transformations in SHE: a formal approach to architecture design","authors":"J. Voeten, P.H.A. van der Putten, M. Stevens","doi":"10.1109/EURMIC.1996.546361","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546361","url":null,"abstract":"SHE (Software/Hardware Engineering) is an object-oriented analysis, specification and design method for complex reactive hardware/software systems. SHE is based on the formal specification language POOSL and a design framework guiding the analysis and design activities. During analysis several graphical models are produced. These models are formalized in a textual representation in the POOSL language. The obtained POOSL description describes both behaviour and initial system structure. During design the initial system structure may have to be adjusted or refined due to architectural constraints and design decisions. For this purpose so-called behaviour-preserving transformations are used. These transformations allow structure modifications in a graphical way and they allow the automatic change of the POOSL specification during interactive system simulation. This paper reports the development of a formal basis for design transformations and shows their applicability.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122276956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Increasing the effective memory bandwidth in multivector processors 增加多矢量处理器的有效内存带宽
A. M. D. Corral, J. Llabería
{"title":"Increasing the effective memory bandwidth in multivector processors","authors":"A. M. D. Corral, J. Llabería","doi":"10.1109/EURMIC.1996.546363","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546363","url":null,"abstract":"In multivector processors, the effective throughput of the memory system is a decisive factor in the performance of the system. The lost cycles due to conflicts between concurrent vector streams make the effective throughput be lower than the peak throughput. When the request rate of all the concurrent vector streams to every memory module is less than or equal to the service rate, conflicts appear because concurrent vector streams reference memory modules in different orders. This paper proposes an access sequence to the vector stream elements that eliminates this kind of conflicts, allowing the effective throughput reach the peak throughput. In other cases, when request rate is greater than the service rate, the proposed order reduces the number of lost cycles, and the effective throughput increases.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127152256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A graph rewriting approach for transformational design of digital systems 数字系统转换设计的图重写方法
C. Huijs
{"title":"A graph rewriting approach for transformational design of digital systems","authors":"C. Huijs","doi":"10.1109/EURMIC.1996.546380","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546380","url":null,"abstract":"Transformational design integrates design and verification. It combines \"correctness by construction\" and design creativity by the use of pre-proven behaviour preserving transformations as design steps. The formal aspects of this methodology are hidden in the transformations. A constraint is the availability of a design representation with a compositional formal semantics. Graph representations are useful design representations because of their visualisation of design information. In this paper graph rewriting theory, as developed in the last twenty years in mathematics, is shown to be a useful basis for a formal framework for transformational design. The semantic aspects of graphs which are no part of graph rewriting theory are included by the use of attributed graphs. The used attribute algebra, table algebra, is a relation algebra derived from database theory. The combination of graph rewriting, table algebra and transformational design is new.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130323528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A formal design and implementation method for real-time embedded systems 实时嵌入式系统的形式化设计与实现方法
S. Bradley, W. Henderson, D. Kendall, A. Robson, Stephen Hawkes
{"title":"A formal design and implementation method for real-time embedded systems","authors":"S. Bradley, W. Henderson, D. Kendall, A. Robson, Stephen Hawkes","doi":"10.1109/EURMIC.1996.546368","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546368","url":null,"abstract":"This paper tackles the problem of using formal methods for practical real-time system development and verification, and is based on a real example. Many formal methods for real-time systems have been proposed but this technique (AORTA) is one of the few to address the issue of how formal designs are to be implemented. Earlier papers on AORTA have been based on providing the formal semantics of the language, and on particular aspects of implementation or verification. This paper concentrates on setting AORTA within the development life cycle, and demonstrating that the approach can be adopted for non-trivial examples.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131222207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Multicast routing algorithms for Manhattan Street Network 曼哈顿街网络的组播路由算法
Hoyoung Hwang, Hyoungjun Kim, Yanghee Choi, Chongsang Kim
{"title":"Multicast routing algorithms for Manhattan Street Network","authors":"Hoyoung Hwang, Hyoungjun Kim, Yanghee Choi, Chongsang Kim","doi":"10.1109/EURMIC.1996.546463","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546463","url":null,"abstract":"In spite of the attractive characteristics of Manhattan Street Network (MSN), it is generally thought that providing multicast services over MSN is inherently difficult. We consider here new multicast routing algorithms for MSN. In the proposed algorithms, packets are routed along a dynamic multicast tree which is determined at each routing time. The detailed algorithms and simulation results are presented in this paper. The performance curves obtained show that the proposed algorithms are feasible and practical solutions for the multicast routing over MSN.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114933807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A general framework for positioning, evaluating and selecting the new generation of development tools 定位、评估和选择新一代开发工具的一般框架
J. Vanthienen, S. Poelmans
{"title":"A general framework for positioning, evaluating and selecting the new generation of development tools","authors":"J. Vanthienen, S. Poelmans","doi":"10.1109/EURMIC.1996.546387","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546387","url":null,"abstract":"This paper focuses on the evaluation and positioning of a new generation of development tools containing subtools (browsers, debuggers, GUI-builders, ...) and programming languages that are designed to work together and have a common graphical user interface and are therefore called environments. Several trends in IT have led to a pluriform range of development tools that can be classified in numerous categories. Examples are: object-oriented tools, GUI-tools, upper and lower CASE-tools, client/server tools and 4GL environments. This classification does not sufficiently cover the tools subject in this paper for the reason that only one criterion is used to distinguish them. The new generation of development environments often fit in several categories because to a certain extent, several criteria can be applied to evaluate them. In this study, we will offer a broad classification scheme with which tools can be positioned and which can be refined through further research.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"130 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120908360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Broadcast with time and causality constraints for multimedia applications 多媒体应用中具有时间和因果关系约束的广播
R. Baldoni, M. Raynal, R. Prakash, M. Singhal
{"title":"Broadcast with time and causality constraints for multimedia applications","authors":"R. Baldoni, M. Raynal, R. Prakash, M. Singhal","doi":"10.1109/EURMIC.1996.546489","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546489","url":null,"abstract":"/spl Delta/-causal ordering is a communication abstraction designed for distributed applications whose messages (i) have to be delivered according to causal ordering and (ii) have a limited lifetime after which their data can no longer be used by the application. Example of such applications are: multimedia real-time collaborative applications and groupware real-time applications. For such applications, the broadcasting of information is of primary importance. In this paper we propose a simple and efficient /spl Delta/-causal ordering protocol in the context of broadcast communication. By taking into account transitive dependencies on message sends, this algorithm gets a significant reduction in the control information piggybacked on application messages, compared to previous algorithms.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124483672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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