阵列算法处理器单元在fpga上的实现

Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies Pub Date : 1996-09-02 DOI:10.1109/EURMIC.1996.546364

István Vassányi, István Erényi

{"title":"阵列算法处理器单元在fpga上的实现","authors":"István Vassányi, István Erényi","doi":"10.1109/EURMIC.1996.546364","DOIUrl":null,"url":null,"abstract":"Recent advances in FPGA technology offer a suitable environment for massively parallel, fine-grain array architectures. The paper gives geometric criteria for an optimal \"jigsaw tessellated\" processor cell, and cost function for cell placement. The paper demonstrates the use of FPGA-based processor arrays by the implementation results of two cellular image processing algorithms. The outlined concepts are being implemented in a placement-routing tool.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Implementation of processor cells for array algorithms on FPGAs\",\"authors\":\"István Vassányi, István Erényi\",\"doi\":\"10.1109/EURMIC.1996.546364\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recent advances in FPGA technology offer a suitable environment for massively parallel, fine-grain array architectures. The paper gives geometric criteria for an optimal \\\"jigsaw tessellated\\\" processor cell, and cost function for cell placement. The paper demonstrates the use of FPGA-based processor arrays by the implementation results of two cellular image processing algorithms. The outlined concepts are being implemented in a placement-routing tool.\",\"PeriodicalId\":311520,\"journal\":{\"name\":\"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies\",\"volume\":\"74 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-09-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURMIC.1996.546364\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURMIC.1996.546364","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

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摘要

FPGA技术的最新进展为大规模并行、细粒度阵列架构提供了合适的环境。本文给出了最优“拼图镶嵌”处理器单元的几何准则，以及单元放置的成本函数。本文通过两种细胞图像处理算法的实现结果，论证了基于fpga的处理器阵列的使用。概述的概念正在放置路由工具中实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Implementation of processor cells for array algorithms on FPGAs

Recent advances in FPGA technology offer a suitable environment for massively parallel, fine-grain array architectures. The paper gives geometric criteria for an optimal "jigsaw tessellated" processor cell, and cost function for cell placement. The paper demonstrates the use of FPGA-based processor arrays by the implementation results of two cellular image processing algorithms. The outlined concepts are being implemented in a placement-routing tool.

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Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies

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