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2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International最新文献

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Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies 晶圆级3D集成与Cu TSV和微碰撞/粘合剂混合粘合技术
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International Pub Date : 2012-08-16 DOI: 10.1109/3DIC.2012.6262949
C. Ko, Z. Hsiao, Y. J. Chang, P. Chen, J. Huang, Hsin-Chia Fu, Y. J. Huang, C. Chiang, W. L. Tsat, Y. -. Chen, W. Lo, Kuan-Neng Chen
{"title":"Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies","authors":"C. Ko, Z. Hsiao, Y. J. Chang, P. Chen, J. Huang, Hsin-Chia Fu, Y. J. Huang, C. Chiang, W. L. Tsat, Y. -. Chen, W. Lo, Kuan-Neng Chen","doi":"10.1109/3DIC.2012.6262949","DOIUrl":"https://doi.org/10.1109/3DIC.2012.6262949","url":null,"abstract":"Cu TSV combination with Cu/Sn micro-joint to form vertical interconnection is a good alternative for 3D integration. The insertion loss of two chip stack was evaluated by simulation to realize the signal transmission effects in high speed digital signaling via TSV and micro-joint interconnect. To satisfy the throughput and cost requirement for mass production in future, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding was demonstrated. Key techniques including TSV fabrication, micro-bumping, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. This paper presents a complete study of structure design, process condition, electrical and reliability assessment of the wafer-level 3D integration scheme. The 3D integration scheme was assessed to be with excellent electrical performance and reliability, and is potentially to be applied for 3D IC applications.","PeriodicalId":308780,"journal":{"name":"2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115623835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Design of capacitive-coupling-based simultaneously bi-directional transceivers for 3DIC 基于电容耦合的3DIC同步双向收发器设计
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International Pub Date : 2012-08-16 DOI: 10.1109/3DIC.2012.6263046
M. Aung, Eric Lim, T. Yoshikawa, T. T. Kim
{"title":"Design of capacitive-coupling-based simultaneously bi-directional transceivers for 3DIC","authors":"M. Aung, Eric Lim, T. Yoshikawa, T. T. Kim","doi":"10.1109/3DIC.2012.6263046","DOIUrl":"https://doi.org/10.1109/3DIC.2012.6263046","url":null,"abstract":"Capacitive-coupling-based simultaneously bidirectional chip-to-chip transceivers for 3DIC are presented. By employing a multi-level signaling strategy with a novel cascaded capacitor configuration, the proposed transceivers can transmit and receive data simultaneously through a single inter-chip coupling capacitor and double the throughput per interconnect without significant overheads in the circuit area and power. In this work, several design and implementation issues such as dead zones, parasitic capacitance, leakage, and coupling effects are addressed. The proposed transceivers are designed and simulated in a commercial 65nm CMOS technology.","PeriodicalId":308780,"journal":{"name":"2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115682260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Cu-based bonding technology for 3D integration applications 三维集成应用的铜基键合技术
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International Pub Date : 2012-08-16 DOI: 10.1109/3DIC.2012.6262974
Kuan-Neng Chen, Z. Xu, F. Liu, C. Ko, Chuan-An Cheng, W. C. Huang, H. L. Lin, C. Cabral, Z. Hsiao, N. Klymko, Hsin-Chia Fu, Y. -. Chen, Jian-Qiang Lu, W. Lo
{"title":"Cu-based bonding technology for 3D integration applications","authors":"Kuan-Neng Chen, Z. Xu, F. Liu, C. Ko, Chuan-An Cheng, W. C. Huang, H. L. Lin, C. Cabral, Z. Hsiao, N. Klymko, Hsin-Chia Fu, Y. -. Chen, Jian-Qiang Lu, W. Lo","doi":"10.1109/3DIC.2012.6262974","DOIUrl":"https://doi.org/10.1109/3DIC.2012.6262974","url":null,"abstract":"This paper summarizes and reports systematical studies of Cu-based bonding technology for 3D IC applications. Hybrid Cu-oxide and Cu-polymer bonding designs and schemes are investigated. Electrical performances and reliability of Cu bond structures provide important guidelines for future 3D IC applications.","PeriodicalId":308780,"journal":{"name":"2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127284302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A miniaturized heterogeneous wireless sensor node in 3DIC 一种小型化的异构无线传感器节点
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International Pub Date : 2012-08-16 DOI: 10.1109/3DIC.2012.6262966
Xin Liu, Lei Wang, M. Jayakrishnan, Jingjing Lan, Hongyu Li, C. Choong, M. Raja, Yong-xin Guo, W. Goh, Jin He, Shan Gao, M. Je
{"title":"A miniaturized heterogeneous wireless sensor node in 3DIC","authors":"Xin Liu, Lei Wang, M. Jayakrishnan, Jingjing Lan, Hongyu Li, C. Choong, M. Raja, Yong-xin Guo, W. Goh, Jin He, Shan Gao, M. Je","doi":"10.1109/3DIC.2012.6262966","DOIUrl":"https://doi.org/10.1109/3DIC.2012.6262966","url":null,"abstract":"In this paper, an innovative design of a miniaturized heterogeneous 3DIC-based wireless sensor node (WSN) is proposed. The design contains stacks of radio frequency (RF) die, mixed-signal die, digital die, and integrated antenna die using the through silicon via (TSV) technology. Significant enhancements to the existing 2D design and verification flow are developed to solve the critical concerns of heterogeneous 3DIC integration, including the block-level partitioning, TSV macro design, the TSV-related modeling and characterization, and physical verification. Solutions are proposed to minimize the electromagnetic interference (EMI) effects between the IC and the antenna. The size of the proposed 3DIC is only 66% as compared to a similar 2D implementation, permitting miniaturization of the complete WSN system.","PeriodicalId":308780,"journal":{"name":"2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125873573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing 具有冗余共享和并行测试的3D存储器的全局内置自我修复
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International Pub Date : 2012-08-16 DOI: 10.1109/3DIC.2012.6262967
Xiaodong Wang, D. Vasudevan, H. Lee
{"title":"Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing","authors":"Xiaodong Wang, D. Vasudevan, H. Lee","doi":"10.1109/3DIC.2012.6262967","DOIUrl":"https://doi.org/10.1109/3DIC.2012.6262967","url":null,"abstract":"3D integration is a promising technology that provides high memory bandwidth, reduced power, shortened latency, and smaller form factor. Among many issues in 3D IC design and production, testing remains one of the major challenges. This paper introduces a new design-for-test technique called 3D-GESP, an efficient Built-In-Self-Repair (BISR) algorithm to fulfill the test and reliability needs for 3D-stacked memories. Instead of the local testing and redundancy allocation method as most current BISR techniques employed, we introduce a global 3D BISR scheme, which not only enables redundancy sharing, but also parallelizes the BISR procedure among all the stacked layers of a 3D memory. Our simulation results show that our proposed technique will significantly increase the memory repair rate and reduce the test time.","PeriodicalId":308780,"journal":{"name":"2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122614338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Impact of containment and deposition method on sub-micron chip-to-wafer self-assembly yield 封装与沉积方式对亚微米晶片自组装良率的影响
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International Pub Date : 2012-08-16 DOI: 10.1109/3DIC.2012.6262953
S. Mermoz, L. Sanchez, L. Cioccio, J. Berthier, E. Deloffre, C. Fretigny
{"title":"Impact of containment and deposition method on sub-micron chip-to-wafer self-assembly yield","authors":"S. Mermoz, L. Sanchez, L. Cioccio, J. Berthier, E. Deloffre, C. Fretigny","doi":"10.1109/3DIC.2012.6262953","DOIUrl":"https://doi.org/10.1109/3DIC.2012.6262953","url":null,"abstract":"3D technologies need a high speed high alignment accuracy chip-to-wafer hybridation technique. This paper will focus on chip-to-wafer self assembly processes coupled with direct bonding hybridation. Submicronic alignment accuracy and a 90 per cent self-assembly process yield are obtained. The self-assembly process yield is analyzed in term of alignment accuracy and direct bonding quality. The impact of the chip's surface state (hydrophilic, hydrophobic, and mixed) on fluid containment efficiency and self-assembly process yield will be discussed. Topological containment (canthotaxis effect) is also evaluated with regards to structures height. Finally, the alignment yield as a function of deposition parameters will be described.","PeriodicalId":308780,"journal":{"name":"2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122983292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Plasma etch and dielectric deposition processes for TSV Reveal 等离子蚀刻和介质沉积TSV Reveal工艺
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International Pub Date : 2012-08-16 DOI: 10.1109/3DIC.2012.6262986
K. Buchanan, D. Thomas, H. Griffiths, Kath Crook, D. Archard, Mark Carruthers, Masahiko Tanaka
{"title":"Plasma etch and dielectric deposition processes for TSV Reveal","authors":"K. Buchanan, D. Thomas, H. Griffiths, Kath Crook, D. Archard, Mark Carruthers, Masahiko Tanaka","doi":"10.1109/3DIC.2012.6262986","DOIUrl":"https://doi.org/10.1109/3DIC.2012.6262986","url":null,"abstract":"Through-Silicon Vias [TSV] offer improved system performance by reducing interconnect length to increase device speeds, and by using stacking to reduce package form-factors and enabling heterogeneous device integration. Via Reveal' [VR] - a sequence of wafer back side process steps - is key to the successful implementation of TSV. After via formation, typically using a via-middle approach, finished CMOS wafers or interposers are temporarily bonded, face-down, to glass carriers. The TSV are then `revealed' using a combination of Si back-grind and plasma etch steps, and then passivated with dielectric. VR processes must maintain acceptably low Total Thickness Variation [TTV] to allow subsequent bonding/stacking steps. Thermal budgets must also be compatible with carrier bonding adhesives - a particular challenge for dielectric deposition. This paper will focus on 300mm plasma etch and low temperature dielectric Plasma Enhanced Chemical Vapour Deposition [PECVD] processes for VR on 300mm substrates.","PeriodicalId":308780,"journal":{"name":"2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122205678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low temperature through-Si via fabrication using electroless deposition 低温硅通孔制造采用化学沉积
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International Pub Date : 2012-08-16 DOI: 10.1109/3DIC.2012.6262984
F. Inoue, H. Philipsen, A. Radisic, S. Armini, P. Leunissen, H. Miyake, R. Arima, Tomohiro Shimizu, Toshiaki Ito, H. Seki, Yuko Shinozaki, Tomohiko Yamamoto, S. Shingubara
{"title":"Low temperature through-Si via fabrication using electroless deposition","authors":"F. Inoue, H. Philipsen, A. Radisic, S. Armini, P. Leunissen, H. Miyake, R. Arima, Tomohiro Shimizu, Toshiaki Ito, H. Seki, Yuko Shinozaki, Tomohiko Yamamoto, S. Shingubara","doi":"10.1109/3DIC.2012.6262984","DOIUrl":"https://doi.org/10.1109/3DIC.2012.6262984","url":null,"abstract":"All-wet fabrication process using electroless deposition of barrier and Cu seed layers has been achieved for a high aspect ratio through-Si via (TSV). Formation of thin barrier metal layer of NiB and CoB is possible by the use of nano particles catalyst which is densely adsorbed on SiO2 of TSV sidewall. Silane coupling agent with 3-aminopropyl-triethoxysilane is effective for enhancement of adsorption density of nanoparticles. Conformal electroless Cu layer is deposited on the barrier layer without catalyst by displacement plating. The adhesion strength between electroless barrier layer and SiO2 substrate is strengthened by annealing. These results strongly suggest a possibility of the all-wet process for high aspect ratio TSV.","PeriodicalId":308780,"journal":{"name":"2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128288519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs 高可靠性和5 μm直径的背面Cu through-silicon Via(TSV)的细尺寸，适用于高可靠性和高端3d lsi
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International Pub Date : 2012-08-16 DOI: 10.1109/3DIC.2012.6262975
Kang-wook Lee, J. Bea, T. Fukushima, Y. Ohara, Tetsu Tanaka, M. Koyanagi
{"title":"High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs","authors":"Kang-wook Lee, J. Bea, T. Fukushima, Y. Ohara, Tetsu Tanaka, M. Koyanagi","doi":"10.1109/3DIC.2012.6262975","DOIUrl":"https://doi.org/10.1109/3DIC.2012.6262975","url":null,"abstract":"The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI was electrically evaluated by capacitance-time (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10-nm and 100-nm thicknesses (at the surface) were fabricated. The C-t curves of the trench capacitors with 10-nm thick Ta layer were severely degraded even after the initial annealing for 5 min at 300°C. It means that Cu atoms diffuse into the active area from the Cu TSV through scallop portions with extremely thin Ta layer in TSVs, and consequently, the generation lifetime of minority carrier is significantly reduced. However, the C-t curves of the trench capacitors with 100-nm thick Ta layer exhibit no change after annealing up to 60min. Based on the C-t evaluation results, we developed high reliable and fine-size of 5-μm diameter backside Cu TSV to achieve high reliability and high-end 3-D LSIs.","PeriodicalId":308780,"journal":{"name":"2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127659885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress 用于3D-LSI的W/Cu tsv具有最小的热机械应力
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International Pub Date : 2012-08-16 DOI: 10.1109/3DIC.2012.6262970
M. Murugesan, H. Hashiguchi, H. Kobayashi, T. Fukushima, Tetsu Tanaka, M. Koyanagi
{"title":"W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress","authors":"M. Murugesan, H. Hashiguchi, H. Kobayashi, T. Fukushima, Tetsu Tanaka, M. Koyanagi","doi":"10.1109/3DIC.2012.6262970","DOIUrl":"https://doi.org/10.1109/3DIC.2012.6262970","url":null,"abstract":"High density 3D-LSI with W-TSV for signal line and Cu-TSV for power/GND line, and Cu-TSV containing W stress absorbing layers were investigated for the induced thermo-mechanical stress in 3D-LSI Si die/wafer after wafer thinning and bonding using micro-Raman spectroscopic technique. Stress mapping analysis revealed that W-TSV has induced less thermo-mechanical stress in LSI Si, whereas the Cu-TSV has induced large amount of stress. Further, Cu-TSV with W stress absorbing layer showed much reduced residual thermo-mechanical stress as compared to the pure Cu-TSV, i.e for 6 μm diameter Cu-TSV with W layer showed <; +100 MPa of tensile stress after heating at 400 °C, whereas the Cu-TSV without W layer revealed >; -300 MPa of compressive stress after heating at 400 °C. This property can be readily employed to minimize the residual thermo-mechanical stress in the bonded high density 3D-LSI.","PeriodicalId":308780,"journal":{"name":"2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115575413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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