2021 International Conference on Computing, Electronic and Electrical Engineering (ICE Cube)最新文献

筛选

英文中文

An On-chip Reconfigurable Multi-layer Perceptron and Recurrent Neural Network Processor for Speech Recognition 用于语音识别的片上可重构多层感知器和递归神经网络处理器

2021 International Conference on Computing, Electronic and Electrical Engineering (ICE Cube) Pub Date : 2021-10-26 DOI: 10.1109/ICECube53880.2021.9628208

Junaid Hussain Muzamal, Anne Kwong, Muhammad Asghar

{"title":"An On-chip Reconfigurable Multi-layer Perceptron and Recurrent Neural Network Processor for Speech Recognition","authors":"Junaid Hussain Muzamal, Anne Kwong, Muhammad Asghar","doi":"10.1109/ICECube53880.2021.9628208","DOIUrl":"https://doi.org/10.1109/ICECube53880.2021.9628208","url":null,"abstract":"Modern voice-based applications, such as speech recognition and classification, mainly exploit the neural network-based algorithms (i.e., Multilayer Perceptron, Recurrent Neural Network, LSTM), and they have established extraordinary promising results in terms of accuracy, especially in sequential data recognition. However, such algorithms involve massive Recurrent Neural Network (RNN) related computations, which are extremely difficult to manage with traditional general-purpose processors. To solve this issue, a Lookup Tables (LUT) based multiplier architecture of accelerators have merged, which comprises a collection of several hundred processing elements (PEs). By exploiting the phenomena of parallel computations, these accelerators accomplish excellent results and high throughput in general. However, already proposed architectures of PEs do not optimize the weight calculation and other parameters that impact the silicon implementation. To this end, we propose an on-chip architecture for the MLP-RNN processor to speed up the matrix multiplication while optimizing the performance, cost, and power consumption with LUT-powered multiplication. Theoretically, we observed a 75% reduction in weight and 5x improvement in power consumption in simulation on 65nm at 200MHz clock 1.2V CMOS process technology","PeriodicalId":308227,"journal":{"name":"2021 International Conference on Computing, Electronic and Electrical Engineering (ICE Cube)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126496540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

首页上一页