Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation最新文献_第2页

Multicore acceleration of priority-based schedulers for concurrency bug detection 用于并发错误检测的基于优先级的调度器的多核加速

Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation Pub Date : 2012-06-11 DOI: 10.1145/2254064.2254128

Santosh Nagarakatte, S. Burckhardt, Milo M. K. Martin, M. Musuvathi

{"title":"Multicore acceleration of priority-based schedulers for concurrency bug detection","authors":"Santosh Nagarakatte, S. Burckhardt, Milo M. K. Martin, M. Musuvathi","doi":"10.1145/2254064.2254128","DOIUrl":"https://doi.org/10.1145/2254064.2254128","url":null,"abstract":"Testing multithreaded programs is difficult as threads can interleave in a nondeterministic fashion. Untested interleavings can cause failures, but testing all interleavings is infeasible. Many interleaving exploration strategies for bug detection have been proposed, but their relative effectiveness and performance remains unclear as they often lack publicly available implementations and have not been evaluated using common benchmarks. We describe NeedlePoint, an open-source framework that allows selection and comparison of a wide range of interleaving exploration policies for bug detection proposed by prior work. Our experience with NeedlePoint indicates that priority-based probabilistic concurrency testing (the PCT algorithm) finds bugs quickly, but it runs only one thread at a time, which destroys parallelism by serializing executions. To address this problem we propose a parallel version of the PCT algorithm~(PPCT). We show that the new algorithm outperforms the original by a factor of 5x when testing parallel programs on an eight-core machine. We formally prove that parallel PCT provides the same probabilistic coverage guarantees as PCT. Moreover, PPCT is the first algorithm that runs multiple threads while providing coverage guarantees.","PeriodicalId":308121,"journal":{"name":"Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125476661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 67

Session details: Performance analysis 会话详细信息:性能分析

Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation Pub Date : 2012-06-11 DOI: 10.1145/3250580

Amer Diwan

引用次数: 0

Scalable and precise dynamic datarace detection for structured parallelism 结构化并行的可伸缩和精确的动态数据检测

Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation Pub Date : 2012-06-11 DOI: 10.1145/2254064.2254127

Raghavan Raman, Jisheng Zhao, Vivek Sarkar, Martin T. Vechev, Eran Yahav

引用次数: 109

Polyhedra scanning revisited 多面体扫描重新开始

Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation Pub Date : 2012-06-11 DOI: 10.1145/2254064.2254123

Chun Chen

引用次数: 55

And then there were none: a stall-free real-time garbage collector for reconfigurable hardware 然后就没有了:一个无失速的实时垃圾收集器，用于可重构硬件

Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation Pub Date : 2012-06-11 DOI: 10.1145/2254064.2254068

D. F. Bacon, P. Cheng, Sunil Shukla

{"title":"And then there were none: a stall-free real-time garbage collector for reconfigurable hardware","authors":"D. F. Bacon, P. Cheng, Sunil Shukla","doi":"10.1145/2254064.2254068","DOIUrl":"https://doi.org/10.1145/2254064.2254068","url":null,"abstract":"Programmers are turning to radical architectures such as reconfigurable hardware (FPGAs) to achieve performance. But such systems, programmed at a very low level in languages with impoverished abstractions, are orders of magnitude more complex to use than conventional CPUs. The continued exponential increase in transistors, combined with the desire to implement ever more sophisticated algorithms, makes it imperative that such systems be programmed at much higher levels of abstraction. One of the fundamental high-level language features is automatic memory management in the form of garbage collection. We present the first implementation of a complete garbage collector in hardware (as opposed to previous \"hardware-assist\" techniques), using an FPGA and its on-chip memory. Using a completely concurrent snapshot algorithm, it provides single-cycle access to the heap, and never stalls the mutator for even a single cycle, achieving a deterministic mutator utilization (MMU) of 100%. We have synthesized the collector to hardware and show that it never consumes more than 1% of the logic resources of a high-end FPGA. For comparison we also implemented explicit (malloc/free) memory management, and show that real-time collection is about 4% to 17% slower than malloc, with comparable energy consumption. Surprisingly, in hardware real-time collection is superior to stop-the-world collection on every performance axis, and even for stressful micro-benchmarks can achieve 100% MMU with heaps as small as 1.01 to 1.4 times the absolute minimum.","PeriodicalId":308121,"journal":{"name":"Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114106903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Diderot: a parallel DSL for image analysis and visualization Diderot:用于图像分析和可视化的并行DSL

Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation Pub Date : 2012-06-11 DOI: 10.1145/2254064.2254079

Charisee Chiw, G. Kindlmann, John H. Reppy, Lamont Samuels, Nicholas Seltzer

{"title":"Diderot: a parallel DSL for image analysis and visualization","authors":"Charisee Chiw, G. Kindlmann, John H. Reppy, Lamont Samuels, Nicholas Seltzer","doi":"10.1145/2254064.2254079","DOIUrl":"https://doi.org/10.1145/2254064.2254079","url":null,"abstract":"Research scientists and medical professionals use imaging technology, such as computed tomography (CT) and magnetic resonance imaging (MRI) to measure a wide variety of biological and physical objects. The increasing sophistication of imaging technology creates demand for equally sophisticated computational techniques to analyze and visualize the image data. Analysis and visualization codes are often crafted for a specific experiment or set of images, thus imaging scientists need support for quickly developing codes that are reliable, robust, and efficient. In this paper, we present the design and implementation of Diderot, which is a parallel domain-specific language for biomedical image analysis and visualization. Diderot supports a high-level model of computation that is based on continuous tensor fields. These tensor fields are reconstructed from discrete image data using separable convolution kernels, but may also be defined by applying higher-order operations, such as differentiation (∇). Early experiments demonstrate that Diderot provides both a high-level concise notation for image analysis and visualization algorithms, as well as high sequential and parallel performance.","PeriodicalId":308121,"journal":{"name":"Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127384657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 78

Automated synthesis of symbolic instruction encodings from I/O samples 从I/O样本自动合成符号指令编码

Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation Pub Date : 2012-06-11 DOI: 10.1145/2254064.2254116

Patrice Godefroid, Ankur Taly

引用次数: 70

Effective parallelization of loops in the presence of I/O operations 在存在I/O操作的情况下有效地并行化循环

Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation Pub Date : 2012-06-11 DOI: 10.1145/2254064.2254122

Min Feng, Rajiv Gupta, Iulian Neamtiu

{"title":"Effective parallelization of loops in the presence of I/O operations","authors":"Min Feng, Rajiv Gupta, Iulian Neamtiu","doi":"10.1145/2254064.2254122","DOIUrl":"https://doi.org/10.1145/2254064.2254122","url":null,"abstract":"Software-based thread-level parallelization has been widely studied for exploiting data parallelism in purely computational loops to improve program performance on multiprocessors. However, none of the previous efforts deal with efficient parallelization of hybrid loops, i.e., loops that contain a mix of computation and I/O operations. In this paper, we propose a set of techniques for efficiently parallelizing hybrid loops. Our techniques apply DOALL parallelism to hybrid loops by breaking the cross-iteration dependences caused by I/O operations. We also support speculative execution of I/O operations to enable speculative parallelization of hybrid loops. Helper threading is used to reduce the I/O bus contention caused by the improved parallelism. We provide an easy-to-use programming model for exploiting parallelism in loops with I/O operations. Parallelizing hybrid loops using our model requires few modifications to the code. We have developed a prototype implementation of our programming model. We have evaluated our implementation on a 24-core machine using eight applications, including a widely-used genomic sequence assembler and a multi-player game server, and others from PARSEC and SPEC CPU2000 benchmark suites. The hybrid loops in these applications take 23%-99% of the total execution time on our 24-core machine. The parallelized applications achieve speedups of 3.0x-12.8x with hybrid loop parallelization over the sequential versions of the same applications. Compared to the versions of applications where only computation loops are parallelized, hybrid loop parallelization improves the application performance by 68% on average.","PeriodicalId":308121,"journal":{"name":"Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123237798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Language-based control and mitigation of timing channels 基于语言的定时通道控制和缓解

Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation Pub Date : 2012-06-11 DOI: 10.1145/2254064.2254078

Danfeng Zhang, Aslan Askarov, A. Myers

引用次数: 139

Parcae: a system for flexible parallel execution 并行:一种灵活的并行执行系统

Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation Pub Date : 2012-06-11 DOI: 10.1145/2254064.2254082

A. Raman, A. Zaks, Jae W. Lee, David I. August

{"title":"Parcae: a system for flexible parallel execution","authors":"A. Raman, A. Zaks, Jae W. Lee, David I. August","doi":"10.1145/2254064.2254082","DOIUrl":"https://doi.org/10.1145/2254064.2254082","url":null,"abstract":"Workload, platform, and available resources constitute a parallel program's execution environment. Most parallelization efforts statically target an anticipated range of environments, but performance generally degrades outside that range. Existing approaches address this problem with dynamic tuning but do not optimize a multiprogrammed system holistically. Further, they either require manual programming effort or are limited to array-based data-parallel programs. This paper presents Parcae, a generally applicable automatic system for platform-wide dynamic tuning. Parcae includes (i) the Nona compiler, which creates flexible parallel programs whose tasks can be efficiently reconfigured during execution; (ii) the Decima monitor, which measures resource availability and system performance to detect change in the environment; and (iii) the Morta executor, which cuts short the life of executing tasks, replacing them with other functionally equivalent tasks better suited to the current environment. Parallel programs made flexible by Parcae outperform original parallel implementations in many interesting scenarios.","PeriodicalId":308121,"journal":{"name":"Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125545251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 54