发布求助
文献互助 智能选刊 最新文献

European Test Workshop 1999 (Cat. No.PR00390)最新文献

筛选
英文 中文
Partial set for flip-flops based on state requirement for non-scan BIST scheme 基于非扫描BIST方案状态要求的触发器部分集
European Test Workshop 1999 (Cat. No.PR00390) Pub Date : 1999-09-24 DOI: 10.1109/ETW.1999.804306
M. Flottes, C. Landrault, A. Petitqueux
{"title":"Partial set for flip-flops based on state requirement for non-scan BIST scheme","authors":"M. Flottes, C. Landrault, A. Petitqueux","doi":"10.1109/ETW.1999.804306","DOIUrl":"https://doi.org/10.1109/ETW.1999.804306","url":null,"abstract":"This paper describes a methodology for improving sequential circuit's testability in a pseudo-random testing environment. Our goal is to slightly modify the circuit under test with a DFT technique. For this, partial reset of circuit's flip-flops is performed during application of the test sequence. Flip-flop candidates far reset and their reset period are chosen according to a methodology based on identification of required test states for hard-to-detect faults. By increasing the probability to reach these states, we improve the fault coverage.","PeriodicalId":302152,"journal":{"name":"European Test Workshop 1999 (Cat. No.PR00390)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124204643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
On avoiding undetectable faults during test generation 在测试生成过程中避免不可检测的故障
European Test Workshop 1999 (Cat. No.PR00390) Pub Date : 1999-09-24 DOI: 10.1109/ETW.1999.804292
I. Pomeranz, S. Reddy
{"title":"On avoiding undetectable faults during test generation","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ETW.1999.804292","DOIUrl":"https://doi.org/10.1109/ETW.1999.804292","url":null,"abstract":"We use a property that distinguishes most of the undetectable faults in a circuit from detectable ones, in order to avoid targeting undetectable faults during test generation. We show that it is possible to avoid most of the undetectable faults until most of the detectable faults are detected. The test generation process is speeded-up by avoiding undetectable faults, since wasted effort expended in trying to detect undetectable faults is avoided. When all or most of the faults that remain undetected by the test generator appear to be undetectable faults, a procedure for identifying undetectable faults may be used. Detectable faults, if any such faults remain, may then be given to the test generator to obtain complete fault coverage. We study the proposed property in conjunction with test generation processes for both combinational and sequential circuits.","PeriodicalId":302152,"journal":{"name":"European Test Workshop 1999 (Cat. No.PR00390)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126253603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Using the BS register for capturing and storing n-bit sequences in real-time 使用BS寄存器实时捕获和存储n位序列
European Test Workshop 1999 (Cat. No.PR00390) Pub Date : 1999-09-24 DOI: 10.1109/ETW.1999.804501
G. Alves, J. Ferreira
{"title":"Using the BS register for capturing and storing n-bit sequences in real-time","authors":"G. Alves, J. Ferreira","doi":"10.1109/ETW.1999.804501","DOIUrl":"https://doi.org/10.1109/ETW.1999.804501","url":null,"abstract":"Boundary Scan test is now widely accepted and used for the structural test of Printed Circuit Boards. However, the more demanding requirements of prototype debug and validation are not sufficiently covered by the mandatory and optional operating modes described in the IEEE 1149.1 Standard. Previous work has focused on this problem, having resulted in a new set of user-defined optional instructions addressing the use of the BS register to store in real-time; a sequence of continuous vectors, captured at its parallel inputs without/until/after a certain condition is found. In this paper we describe the trade-off between input channels and storage capacity, by proposing a new operating mode where the BS register is used to capture/store an n-bit sequence captured at one single functional pin. We also describe how this operating mode can be further extended into the P1149.4 domain, for capturing/storing the n-bit data stream generated by a /spl Sigma//spl Delta/ converter placed in the TBIC.","PeriodicalId":302152,"journal":{"name":"European Test Workshop 1999 (Cat. No.PR00390)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128579388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On calculating efficient LFSR seeds for built-in self test 内建自检有效LFSR种子的计算
European Test Workshop 1999 (Cat. No.PR00390) Pub Date : 1999-09-24 DOI: 10.1109/ETW.1999.803819
C. Fagot, O. Gascuel, P. Girard, C. Landrault
{"title":"On calculating efficient LFSR seeds for built-in self test","authors":"C. Fagot, O. Gascuel, P. Girard, C. Landrault","doi":"10.1109/ETW.1999.803819","DOIUrl":"https://doi.org/10.1109/ETW.1999.803819","url":null,"abstract":"Linear Feedback Shift Registers (LFSRs) are commonly used as pseudo-random test pattern generators (TPGs) in BIST schemes. This paper presents a fast simulation-based method to compute an efficient seed (initial state) of a given primitive polynomial LFSR TPG. The size of the LFSR, the primitive feedback polynomial and the length of the generated test sequence are a priori known. The method uses a deterministic test cube compression technique and produces a one-seed LFSR test sequence of a predefined test length that achieves high fault coverage. This technique can be applied either in pseudo-random testing for BISTed circuits containing few random resistant faults, or in pseudo-deterministic BIST where it allows the hardware generator overhead area to be reduced. Compared with existing methods, the proposed technique is able to deal with combinational circuits of great size and with a lot of primary inputs. Experimental results demonstrate the effectiveness of our method.","PeriodicalId":302152,"journal":{"name":"European Test Workshop 1999 (Cat. No.PR00390)","volume":"8 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114122047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study 基于sram的fpga逻辑单元的测试配置最小化:一个案例研究
European Test Workshop 1999 (Cat. No.PR00390) Pub Date : 1999-09-24 DOI: 10.1109/ETW.1999.804520
M. Renovell, J. Portal, J. Figueras, Y. Zorian
{"title":"Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study","authors":"M. Renovell, J. Portal, J. Figueras, Y. Zorian","doi":"10.1109/ETW.1999.804520","DOIUrl":"https://doi.org/10.1109/ETW.1999.804520","url":null,"abstract":"This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA. The proposed approach concerns the XILINX4000 family. On this example of FPGA, a classical test technique consists in first generating test configurations for the elementary modules, then test configurations for a single logic cell, and finally test configurations for the m/spl times/m array of logic cells. In this classical technique, it is shown that the key point is the minimization of the number of test configurations for a logic cell. An approach for the logic cell of the XILINX4000 family is then described to define a minimum number of test configurations. This approach gives only 5 test configurations for the XILINX4000 family while the previous published works concerning Boolean testing of this FPGA family gives 8 or 21 test configurations.","PeriodicalId":302152,"journal":{"name":"European Test Workshop 1999 (Cat. No.PR00390)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125959664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A new approach for the nonlinearity test of ADCs/DACs and its application for BIST 一种adc / dac非线性测试的新方法及其在BIST中的应用
European Test Workshop 1999 (Cat. No.PR00390) Pub Date : 1999-09-24 DOI: 10.1109/ETW.1999.804206
F. Xu
{"title":"A new approach for the nonlinearity test of ADCs/DACs and its application for BIST","authors":"F. Xu","doi":"10.1109/ETW.1999.804206","DOIUrl":"https://doi.org/10.1109/ETW.1999.804206","url":null,"abstract":"This paper describes an algorithm to derive the nonlinearity performances of Analog-to-Digital and Digital-to-Analog Converters (ADCs/DACs) from FFT results. The main advantages of the new approach over conventional ones are that the test stimuli are simpler and the influence of noise on test results decreases. This method is especially useful for the BIST of converters. Experiments have shown the feasibility of this approach.","PeriodicalId":302152,"journal":{"name":"European Test Workshop 1999 (Cat. No.PR00390)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122222428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Design of an automatic testing for FPGAs fpga的自动测试设计
European Test Workshop 1999 (Cat. No.PR00390) Pub Date : 1999-09-24 DOI: 10.1109/ETW.1999.804522
A. Doumar, T. Ohmameuda, Hideo Ito
{"title":"Design of an automatic testing for FPGAs","authors":"A. Doumar, T. Ohmameuda, Hideo Ito","doi":"10.1109/ETW.1999.804522","DOIUrl":"https://doi.org/10.1109/ETW.1999.804522","url":null,"abstract":"This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original SRAM part is modified a bit so that the FPGA gets the ability to automatically shift the data on-chip and then the test becomes faster. This method does not need a large outside memory (off-chip memory) for saving the test data. It is proved that this method detects multiple faults and covers 100%; of modeled faults. The simulation results of Xilinix XC4000 family, using CAD tools, shows that the routing and the placement of this method are easily achieved.","PeriodicalId":302152,"journal":{"name":"European Test Workshop 1999 (Cat. No.PR00390)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132846180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Functional and structural testing of switched-current circuits 开关电流电路的功能和结构测试
European Test Workshop 1999 (Cat. No.PR00390) Pub Date : 1999-09-24 DOI: 10.1109/ETW.1999.803821
M. Renovell, F. Azaïs, J.-C. Bodin, Y. Bertrand
{"title":"Functional and structural testing of switched-current circuits","authors":"M. Renovell, F. Azaïs, J.-C. Bodin, Y. Bertrand","doi":"10.1109/ETW.1999.803821","DOIUrl":"https://doi.org/10.1109/ETW.1999.803821","url":null,"abstract":"This paper aims at defining an efficient test strategy for switched-current circuit testing. Taking into account the specificity of these circuits, we propose an original structural test technique as an alternative to traditionally-used functional verification. This technique is validated both at the cell and block levels. Test results demonstrate that a high fault coverage can be achieved with a low cost test procedure. A mixed strategy combining benefits of functional and structural approaches is derived.","PeriodicalId":302152,"journal":{"name":"European Test Workshop 1999 (Cat. No.PR00390)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130073121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
On the fault-injection-caused increase of the DAE-index in analogue fault simulation 模拟故障模拟中故障注入引起的dae指数增大
European Test Workshop 1999 (Cat. No.PR00390) Pub Date : 1999-09-24 DOI: 10.1109/ETW.1999.804423
B. Straube, K. Reinschke, W. Vermeiren, K. Röbenack, Bert Müller, C. Clauß
{"title":"On the fault-injection-caused increase of the DAE-index in analogue fault simulation","authors":"B. Straube, K. Reinschke, W. Vermeiren, K. Röbenack, Bert Müller, C. Clauß","doi":"10.1109/ETW.1999.804423","DOIUrl":"https://doi.org/10.1109/ETW.1999.804423","url":null,"abstract":"This paper demonstrates the possibility of the occurrence of numerical problems in analogue fault simulation due to a fault-injection-caused increase of the DAE-index. Based on analytical results and fault simulation experiments with two electrical networks it is shown that a network showing no numerical problems during its fault-free simulations may increase its index as a result of the injection of a fault. The higher index causes numerical problems during the simulation. Some suggestions to tackle such index problems are discussed.","PeriodicalId":302152,"journal":{"name":"European Test Workshop 1999 (Cat. No.PR00390)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114666809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A scalable BIST architecture for delay faults 针对延迟故障的可伸缩BIST架构
European Test Workshop 1999 (Cat. No.PR00390) Pub Date : 1999-09-24 DOI: 10.1109/ETW.1999.804299
Martin Keim, I. Polian, H. Hengster, B. Becker
{"title":"A scalable BIST architecture for delay faults","authors":"Martin Keim, I. Polian, H. Hengster, B. Becker","doi":"10.1109/ETW.1999.804299","DOIUrl":"https://doi.org/10.1109/ETW.1999.804299","url":null,"abstract":"We present a scalable BIST (Built-In Self Test) architecture that provides a tunable trade-off between on-chip area demand and test execution time for delay fault testing. So, the architecture can meet test execution time requirements, area requirements, or any target in between. Experiments show the scalability of our approach, e.g., that considerably shorter test execution time can be achieved by storing only a few additional input vectors of the BIST architecture. The gain of test execution time possible with the proposed method ranges from a factor of 2 up to a factor of more than 800000.","PeriodicalId":302152,"journal":{"name":"European Test Workshop 1999 (Cat. No.PR00390)","volume":"31 18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116364948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书