{"title":"HBM: Memory solution for bandwidth-hungry processors","authors":"Joonyoung Kim, Younsu Kim","doi":"10.1109/HOTCHIPS.2014.7478812","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2014.7478812","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on the special features, system design and architectures, memory management and support for processors, and targeted markets for SK Hynix Inc.'s HBM, next generation memory family of products.","PeriodicalId":299263,"journal":{"name":"2014 IEEE Hot Chips 26 Symposium (HCS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126784296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Barkatullah, T. Hanke, R. Iyengar, R. Lewelling, Jim O'Connor
{"title":"Goldstrike 1: Cointerra's first generation crypto-currency processor for bitcoin mining machines","authors":"J. Barkatullah, T. Hanke, R. Iyengar, R. Lewelling, Jim O'Connor","doi":"10.1109/HOTCHIPS.2014.7478824","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2014.7478824","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on the special features, system design and architectures, processing capabilities, and targeted markets for CoinTerra's Goldstrike, a first generation crypto-currency processor for Bitcoin mining machines.","PeriodicalId":299263,"journal":{"name":"2014 IEEE Hot Chips 26 Symposium (HCS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125232801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi
{"title":"High-level synthesis of memory bound and irregular parallel applications with Bambu","authors":"Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi","doi":"10.1109/HOTCHIPS.2014.7478841","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2014.7478841","url":null,"abstract":"Presents a conference poster that addresses high-level synthesis of memory bound and irregular parallel applications.","PeriodicalId":299263,"journal":{"name":"2014 IEEE Hot Chips 26 Symposium (HCS)","volume":"325 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133042694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Applying AMD's Kaveri APU for heterogeneous computing","authors":"Dan Bouvier, B. Sander","doi":"10.1109/HOTCHIPS.2014.7478810","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2014.7478810","url":null,"abstract":"With HSA features, Kaveri is an optimized platform for heterogeneous computing. HSA features make Kaveri the first full OpenCL 2.0 capable chip: fine grained SVM (hUMA); C11 atomics (platform atomics); dynamic parallelism (hQ); pipes (hUMA, hQ).","PeriodicalId":299263,"journal":{"name":"2014 IEEE Hot Chips 26 Symposium (HCS)","volume":"131 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124251896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Have your cake in parallel and eat it sequentially too! Semantically sequential, parallel execution of multiprocessor programs","authors":"G. Gupta","doi":"10.1109/HOTCHIPS.2014.7478839","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2014.7478839","url":null,"abstract":"Multiprocessors are ubiquitous, but programming them continues to to be challenging. Our goal is to simplify multiprocessor programming without compromising performance.","PeriodicalId":299263,"journal":{"name":"2014 IEEE Hot Chips 26 Symposium (HCS)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127849957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Mitigating exploits, rootkits and advanced persistent threats","authors":"David M. Durham","doi":"10.1109/HOTCHIPS.2014.7478798","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2014.7478798","url":null,"abstract":"Presents a collection of slides that address the topic of computer security. Addresses some of the following topics: attacks that are becoming increasingly sophisticated; malware signatures; major areas of vulnerability; and applications and programs for better network and computer security.","PeriodicalId":299263,"journal":{"name":"2014 IEEE Hot Chips 26 Symposium (HCS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128138915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Kamohara, N. Sugii, K. Ishibashi, K. Usami, H. Amano, Kazutoshi Kobayashi, C. Pham
{"title":"A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode","authors":"S. Kamohara, N. Sugii, K. Ishibashi, K. Usami, H. Amano, Kazutoshi Kobayashi, C. Pham","doi":"10.1109/HOTCHIPS.2014.7478838","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2014.7478838","url":null,"abstract":"Presents a conference poster that addresses a perpetuum mobile 32bit central processing unit that resides on 65nm CMOS technology using reverse-body-bias via assisted sleep mode.","PeriodicalId":299263,"journal":{"name":"2014 IEEE Hot Chips 26 Symposium (HCS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131420353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}