26th Annual Symposium on Foundations of Computer Science (sfcs 1985)最新文献

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Byzantine agreement in constant expected time 恒定预期时间的拜占庭协议
26th Annual Symposium on Foundations of Computer Science (sfcs 1985) Pub Date : 1985-10-21 DOI: 10.1109/SFCS.1985.14
Paul Feldman, S. Micali
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引用次数: 28
Simulating two pushdown stores by one tape in O(n1.5v) time 在0 (n1.5v)的时间内,通过一个磁带模拟两个下推存储
26th Annual Symposium on Foundations of Computer Science (sfcs 1985) Pub Date : 1985-10-21 DOI: 10.1109/SFCS.1985.50
Ming Li
{"title":"Simulating two pushdown stores by one tape in O(n1.5v) time","authors":"Ming Li","doi":"10.1109/SFCS.1985.50","DOIUrl":"https://doi.org/10.1109/SFCS.1985.50","url":null,"abstract":"Based on two graph separator theorems, we present two unexpected upper bounds and resolve several open problems for on-line computations. (1) 1 tape nondeterministic machines can simulate 2 pushdown stores in time O(n1.5√logn) (true for both on-line and off-line machines). Together with the Ω(n1.5/√logn) lower bound, this solves the open problem 1 in [DGPR] for the 1 tape vs. 2 pushdown case. It also disproves the commonly conjectured Ω(n2) lower bound. (2) The languages defined by Maass and Freivalds, aimed to obtain optimal lower bound for 1 tape nondeterministic machines, can be accepted in O(n2loglogn√logn) and O(n1.5√logn) time by a 1 tape TM, respectively. (3) 3 pushdown stores are better than 2 pushdown stores. This answers a rather old open problem by Book and Greibach, and Duris and Galil. An Ω(n4/3/loge n) lower bound is also obtained. (4) 1 tape can nondeterministically simulate 1 queue in O(n1.5/√logn) time. This disproves the conjectured Ω(n2) lower bound. Also 1 queue can simulate 2 pushdowns in time O(n1.5√logn).","PeriodicalId":296739,"journal":{"name":"26th Annual Symposium on Foundations of Computer Science (sfcs 1985)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128158719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Area penalty for sublinear signal propagation delay on chip 芯片上亚线性信号传播延迟的面积惩罚
26th Annual Symposium on Foundations of Computer Science (sfcs 1985) Pub Date : 1985-08-01 DOI: 10.1109/SFCS.1985.10
P. Vitányi
{"title":"Area penalty for sublinear signal propagation delay on chip","authors":"P. Vitányi","doi":"10.1109/SFCS.1985.10","DOIUrl":"https://doi.org/10.1109/SFCS.1985.10","url":null,"abstract":"Sublinear signal propagation delay in VLSI circuits carries a far greater penalty in wire area than is commonly realized. Therefore, the global complexity of VLSI circuits is more layout dependent than previously thought. This effect will be truly pronounced in the emerging wafer scale integration technology. We establish lower bounds on the trade-off between sublinear signalling speed and layout area for the implementation of a complete binary tree in VLSI. In particular, sublinear delay can only be realized at the cost of superlinear area. Designs with equal length wires can either not be laid out at all, viz. for logarithmic delay, or require such long wires in the case of radical delay (i.e., rth root of the wire length) that the aimed for gain in speed is cancelled. Also for wire length distributions commonly occurring on chip it appears that the requirements for sublinear signal propagation delay tend to cancel the gain.","PeriodicalId":296739,"journal":{"name":"26th Annual Symposium on Foundations of Computer Science (sfcs 1985)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115640645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Dynamic monotone priorities on planar sets 平面集合上的动态单调优先级
26th Annual Symposium on Foundations of Computer Science (sfcs 1985) Pub Date : 1985-07-01 DOI: 10.1109/SFCS.1985.21
M. Fischer, M. Paterson
{"title":"Dynamic monotone priorities on planar sets","authors":"M. Fischer, M. Paterson","doi":"10.1109/SFCS.1985.21","DOIUrl":"https://doi.org/10.1109/SFCS.1985.21","url":null,"abstract":"A monotonic priority set is a new data structure which supports maximum-finding and deletions over a set of weighted points in the plane. Global updates to the weights can also be made, incrementing the weights of all points above a given threshold in one of the coordinates. The weights are assumed to be always monotonic in both coordinates. An efficient implementation of this structure is presented and two main applications are described. The first is to the problem of optimal assembly of code for computers with two kinds of jump instruction: long and short. The task in the second application is the implementation of a queuing discipline based on the ranks with respect to two different criteria.","PeriodicalId":296739,"journal":{"name":"26th Annual Symposium on Foundations of Computer Science (sfcs 1985)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1985-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127306127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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