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A CMOS oversampled closed-loop DAC with embedded filtering 带嵌入式滤波的CMOS过采样闭环DAC
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6691064
Xinying Ding, D. Su, B. Wooley
{"title":"A CMOS oversampled closed-loop DAC with embedded filtering","authors":"Xinying Ding, D. Su, B. Wooley","doi":"10.1109/ASSCC.2013.6691064","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691064","url":null,"abstract":"A closed-loop oversampled DAC with embedded reconstruction filtering has been integrated in 0.18-μm CMOS. The architecture provides multi-bit conversion without DEM and 3rd-order filtering of out-of-band noise. At a sampling rate of 10MHz with an OSR of 16, the DAC achieves 61-dB SNDR, 63-dB DR, and 50-dB out-of-band noise suppression, while dissipating 22mW from a 1.2-V supply.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116642201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A hysteretic boost regulator with Emulated-Ramp Feedback (ERF) current-sensing technique for LED driving applications 一种用于LED驱动应用的具有仿真斜坡反馈(ERF)电流传感技术的滞后升压调节器
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6690982
Jhih-Sian Guo, Shih-Mei Lin, Chien-Hung Tsai
{"title":"A hysteretic boost regulator with Emulated-Ramp Feedback (ERF) current-sensing technique for LED driving applications","authors":"Jhih-Sian Guo, Shih-Mei Lin, Chien-Hung Tsai","doi":"10.1109/ASSCC.2013.6690982","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690982","url":null,"abstract":"An inductor switching hysteretic control boost DC-DC regulator is presented in this paper with a newly proposed current-sensing technique named “Emulated-Ramp Feedback, ERF”. A boost regulator with a chip verification which achieves a simple structure and low cost is presented for LED driving applications. The regulator was fabricated in a TSMC 0.25μm high voltage (HV) CMOS process with a specification of 5V to 12V in a 0-300mA load range. And a peak efficiency of 92.1% is achieved with only 1.014mm2 chip area.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131871396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A fast and energy-efficient level shifter with wide shifting range from sub-threshold up to I/O voltage 具有从亚阈值到I/O电压的宽移位范围的快速节能电平移位器
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6691001
Jun Zhou, Chao Wang, Xin Liu, Xin Zhang, M. Je
{"title":"A fast and energy-efficient level shifter with wide shifting range from sub-threshold up to I/O voltage","authors":"Jun Zhou, Chao Wang, Xin Liu, Xin Zhang, M. Je","doi":"10.1109/ASSCC.2013.6691001","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691001","url":null,"abstract":"This paper presents a fast and energy-efficient current mirror based level shifter with wide shifting range from sub-threshold voltage up to I/O voltage. Small delay and low power consumption are achieved by addressing the non-full output swing and charge sharing issues in the level shifter from [4]. The measurement results show that the proposed level shifter can convert from 0.21V up to 3.3V with significantly improved delay and power consumption over the existing level shifters. Compared with [4], the maximum reduction of delay, switching energy and leakage power are 3X, 19X, 29X respectively when converting 0.3V to a higher voltage between 0.6V and 3.3V.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127661063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ modulator with digital I/Q calibration for GNSS receivers 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ调制器，带数字I/Q校准，用于GNSS接收机
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6691065
Zehong Zhang, Yang Xu, Nan Qi, B. Chi
{"title":"A 5/20MHz-BW 4.2/8.1mW CT QBP ΣΔ modulator with digital I/Q calibration for GNSS receivers","authors":"Zehong Zhang, Yang Xu, Nan Qi, B. Chi","doi":"10.1109/ASSCC.2013.6691065","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691065","url":null,"abstract":"This paper presents a dual-mode 2nd-order, multi-bit reconfigurable continuous-time quadrature bandpass sigma-delta (CT QBP ΣΔ) modulator employing power scaling technique (PST) for low-IF GNSS receivers. The proposed modulator is capable of supporting both narrow band (NB) of 5MHz bandwidth (BW) and wideband (WB) of 20MHz BW with sampling frequencies of 160MHz and 480MHz, respectively. To solve the instability issue caused by the excess loop delay (ELD) in WB mode, an additional DAC is directly feedback to the input of a summing amplifier and the ELD is fixed to half of the sampling period. Digital I/Q calibration after the decimation is employed to improve the image-rejection ratio (IRR). Implemented in 65nm CMOS, the modulator achieves 65.9/53.7dB SNDR, 76.7/65.9dB SFDR and more than 60dB IRR after calibration across 5/20MHz BW with center frequencies of 4/12MHz. Powered by a 1.2-V supply, the modulator consumes 3.5/6.8mW, resulting in FOMs of 264/516fJ/conversion.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129730702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A wireless power management and data telemetry circuit module for high compliance voltage electrical stimulation applications 一种适用于高电压电刺激应用的无线电源管理和数据遥测电路模块
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6691030
Jianming Zhao, Lei Yao, Rui-Feng Xue, Li Peng, M. Je, Y. Xu
{"title":"A wireless power management and data telemetry circuit module for high compliance voltage electrical stimulation applications","authors":"Jianming Zhao, Lei Yao, Rui-Feng Xue, Li Peng, M. Je, Y. Xu","doi":"10.1109/ASSCC.2013.6691030","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691030","url":null,"abstract":"A wireless power management and data telemetry circuit module for high compliance voltage electrical stimulation applications is presented in this paper. The system consists of rectifier, LDOs, DC-DC step-up charge pump and power monitoring circuit for closed loop wireless power management. The system also consists of a clock and data recovery (CDR) circuit and load shift keying (LSK) modulator for bidirectional data telemetry. The system operates at 13.56MHz. The wireless power management block receives AC power through an implantable coil and outputs three DC levels: 1V, 1.8V and 10V. The CDR circuit recovers clock and data from the 13.56MHz RF carrier through the same coil. The power efficiency of the wireless power management system is measured as 42% with 100μA current load connected on each supply output. The forward and backward data rate of the data telemetry achieves 61.5 kbps and 33.3 kbps, respectively. The system is implemented in 0.18μm CMOS process with 24V HV LDMOS option, occupying a core area of 1.8 mm × 1.8 mm.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129082339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An adaptive integration time CMOS image sensor with multiple readout channels for star trackers 一种具有多读出通道的自适应集成时间CMOS图像传感器
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6690992
Xinyuan Qian, Hang Yu, Shoushun Chen, K. Low
{"title":"An adaptive integration time CMOS image sensor with multiple readout channels for star trackers","authors":"Xinyuan Qian, Hang Yu, Shoushun Chen, K. Low","doi":"10.1109/ASSCC.2013.6690992","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690992","url":null,"abstract":"In this work, we present an adaptive integration time CMOS image sensor with multiple readout channels for star tracker application. The sensor architecture allows each pixel to have an adaptive integration time. By cyclically selecting a row of pixels and checking the integration voltage of each pixel, brighter pixels can be “marked” and read out first. The dimmer pixels will continue integration until their voltage fall into a window defined by two threshold voltages. Each pixel only consists of five transistors. In order to improve the readout throughput and hence to reduce the rolling time, a multiple readout channel architecture is proposed. A proof-of-concept 320×128-pixel image sensor has been implemented using GlobalFoundries 0.18μm mixed-signal CMOS process.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125947866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 13-pJ/bit 900-MHz QPSK/16-QAM transmitter with band shaping for biomedical application 一种13 pj /bit 900 mhz QPSK/16-QAM发射机，带带整形，用于生物医学应用
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6691014
Xiayun Liu, Mehran M. Izad, L. Yao, C. Heng
{"title":"A 13-pJ/bit 900-MHz QPSK/16-QAM transmitter with band shaping for biomedical application","authors":"Xiayun Liu, Mehran M. Izad, L. Yao, C. Heng","doi":"10.1109/ASSCC.2013.6691014","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691014","url":null,"abstract":"A 900-MHz QPSK/16-QAM transmitter targeted for biomedical application is proposed. Injection locking coupled with direct quadrature modulation at PA provides an efficient way to achieve band shaped QPSK/16-QAM modulation with effective side lobe suppression more than 38 dB. Fabricated in a 65-nm CMOS process, the TX can achieve maximum data rate of 50 Mbps/100 Mbps for QPSK/16-QAM with 6% EVM while occupying only 0.08 mm2. Under 0.77-V supply, the TX achieves 26 pJ/bit and 13 pJ/bit respectively with and without activating band shaping.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131233958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 27-nV/√Hz 0.015-mm2 three-stage operational amplifier with split active-feedback compensation 一个27 nv /√Hz 0.015 mm2三级运算放大器，分体式有源反馈补偿
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6691058
Hicham Haibi, I. Akita, M. Ishida
{"title":"A 27-nV/√Hz 0.015-mm2 three-stage operational amplifier with split active-feedback compensation","authors":"Hicham Haibi, I. Akita, M. Ishida","doi":"10.1109/ASSCC.2013.6691058","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691058","url":null,"abstract":"This paper presents a low-noise small-area three-stage operational amplifier using split active-feedback compensation (SAFC) which is suitable for biomedical arrayed sensors. The proposed SAFC amplifier only requires a small capacitance for phase compensation, while it can achieve a low input-referred noise by increasing the first-stage transconductance without sacrificing the phase margin. The proposed SAFC amplifier has been implemented using a standard 0.18-μm CMOS process. The measurement results show that the proposed SAFC amplifier achieves >120-dB DC gain, 6.2-MHz gain bandwidth product, and phase margin of 60°. The measured input-referred noise is 27 nV/√Hz. The current dissipation is measured as 177 μA at a power supply of 1.5 V and it achieves a noise efficiency factor of 14.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131965673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A mm-wave 40 nm CMOS subharmonically injection-locked QVCO with lock detection 带锁检测的毫米波40nm CMOS亚谐波注入锁定QVCO
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6691072
G. Mangraviti, B. Parvais, Qixian Shi, V. Vidojkovic, M. Libois, G. Vandersteen, P. Wambacq
{"title":"A mm-wave 40 nm CMOS subharmonically injection-locked QVCO with lock detection","authors":"G. Mangraviti, B. Parvais, Qixian Shi, V. Vidojkovic, M. Libois, G. Vandersteen, P. Wambacq","doi":"10.1109/ASSCC.2013.6691072","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691072","url":null,"abstract":"This paper demonstrates a 40 nm CMOS mm-wave subharmonically injection-locked QVCO with a lock detection mechanism. The locking range is more than 2GHz over the 55-63 GHz tuning range. An envelope detector simplifies the calibration of the QVCO. In addition, the lock detector, based on passive mixing, detects the lock condition simply by a change in the DC operating point. The large locking range, the large tunability and the combination of envelope detector and lock detector offer a simple approach for robust mm-wave frequency synthesis based on subharmonic injection locking.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134309702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A cooperative power management with auto-configured multi-phase control and real-time power module swap 具有自动配置多相控制和实时电源模块交换的协作电源管理
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6690980
Jen-Huan Tsai, Shin-Jie Huang, Poting Lan, Po-Chiun Huang
{"title":"A cooperative power management with auto-configured multi-phase control and real-time power module swap","authors":"Jen-Huan Tsai, Shin-Jie Huang, Poting Lan, Po-Chiun Huang","doi":"10.1109/ASSCC.2013.6690980","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690980","url":null,"abstract":"For high power efficiency and better signal integrity, distributed power modules with sophisticated management control are popular in modern SiP, SoC and 3D-IC designs. To dynamically and extensively utilize the idle and redundant power modules, this work applies a cooperative concept for on-chip power management. Current control is used to balance the load for distributed power modules. An estimator with digital engine executes intelligent actions such as real-time adding/dropping power modules depending on load and thermal conditions. It automatically configures the power system with proper phase interleaving. In the prototype chip using 0.35-μm CMOS, four modules are connected as a cooperative power network to convert 2.7V to 4.3V input to 1.8V output voltage with less than 25mV ripple. PFM achieves 76% efficiency under 20mA load. 88% power efficiency in PWM with four cooperative modules is 8.5% higher than that with single module under 300mA load.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114829246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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