2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)最新文献

Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs 碳纳米管场效应管多值逻辑门设计及可靠性分析

2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2012-07-04 DOI: 10.1145/2765491.2765515

Jinghang Liang, Jie Han, Linbin Chen, F. Lombardi

引用次数: 12

Irreversibility induced density limits and logical reversiblity in nanocircuits 纳米电路中的不可逆性诱导密度限制和逻辑可逆性

2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2012-07-04 DOI: 10.1145/2765491.2765501

Ismo Hänninen, J. Takala

{"title":"Irreversibility induced density limits and logical reversiblity in nanocircuits","authors":"Ismo Hänninen, J. Takala","doi":"10.1145/2765491.2765501","DOIUrl":"https://doi.org/10.1145/2765491.2765501","url":null,"abstract":"Logical irreversibility will be an important factor to consider in nanocircuits, which reach gate density and operating frequency in the regime of the recently experimentally proven Landauer's Principle. The resulting heat density will limit the performance of classical digital circuits implemented with nanoscale components, when other heat factors are minimized, as in the predicted highly energy-efficient emerging technologies. We demonstrate this effect by calculating the expected logic and heat densities of various computer arithmetic units proposed for quantum-dot cellular automata, which is a computing paradigm offering molecular implementations and ultra-high signal energy conservation. The predicted worst case maximum operating frequencies are one or two orders of magnitude lower than the inherent technology switching rate of the molecular implementations, but increasing the degree of logical reversiblity may alleviate the problem. These results confirm that circuit design for the emerging technologies must account for irreversibility and the Landauer's Principle, which governs all high density and high energy-efficency post-CMOS technologies.","PeriodicalId":287602,"journal":{"name":"2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115506369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Room temperature double gate Single Electron Transistor based standard cell library 基于室温双栅单电子晶体管的标准电池库

2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2012-07-04 DOI: 10.1145/2765491.2765518

Mohamed Amine-Bounouar, A. Beaumont, K. E. Hajjam, F. Calmon, D. Drouin

引用次数: 9

Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices NBTI对FinFET sram影响的统计可靠性分析及采用独立栅极器件的缓解技术

2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2012-07-04 DOI: 10.1145/2765491.2765512

Yao Wang, S. Cotofana, Liang Fang

{"title":"Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices","authors":"Yao Wang, S. Cotofana, Liang Fang","doi":"10.1145/2765491.2765512","DOIUrl":"https://doi.org/10.1145/2765491.2765512","url":null,"abstract":"As planar MOSFETs is approaching its physical scaling limits, FinFET becomes one of the most promising alternative structure to keep on the industry scaling-down trend for future technology generations of 22 nm and beyond. In this paper, we propose a statistical model of Negative Bias Temperature Instability (NBTI) tailored for FinFET SRAM Arrays. The model build upon an extension of the reaction-diffusion theory such that it can cover the natural variations encountered in nanoscale MOSFET circuits. Dynamic NBTI stress on SRAM cells is modeled by using stochastic input signals. A mitigation technology for minimizing the NBTI aging is also demonstrated by taking advantage of the independent-gate FinFET device structure using threshold voltage adjustment. We evaluated the impact of our proposal on the RAM stability by means of SPICE simulations with the BSIM-IMGModel for 22nm FinFET devices. Our simulations conducted at an accelerated temperature 125°C for 108 seconds (~3 years) indicate that a Vth compensation of 0.2V can almost preserve the WRITE and HOLD stability of the fresh device even after 3 years, while for the READ stability the compensation mechanism is less effective. However, the READ Static Noise Margin (SNM) experiences an insignificant decrease over the 3 years time span in the presence of a Vth compensation, while without compensation it decreases by a x4 factor. Thus we can conclude that the proposed technique can improve the stability of SRAM array during its operational life, hence improve the performance and reliability of the system.","PeriodicalId":287602,"journal":{"name":"2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134575592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

ToPoliNano: Nanoarchitectures design made real ToPoliNano:纳米架构设计成为现实

2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2012-07-04 DOI: 10.1145/2765491.2765520

S. Frache, D. Chiabrando, M. Graziano, F. Riente, G. Turvani, M. Zamboni

{"title":"ToPoliNano: Nanoarchitectures design made real","authors":"S. Frache, D. Chiabrando, M. Graziano, F. Riente, G. Turvani, M. Zamboni","doi":"10.1145/2765491.2765520","DOIUrl":"https://doi.org/10.1145/2765491.2765520","url":null,"abstract":"Many facts about emerging nanotechnologies are yet to be assessed. There are still major concerns, for instance, about maximum achievable device density, or about which architecture is best fit for a specific application. Growing complexity requires taking into account many aspects of technology, application and architecture at the same time. Researchers face problems that are not new per se, but are now subject to very different constraints, that need to be captured by design tools. Among the emerging nanotechnologies, two-dimensional nanowire based arrays represent promising nanostructures, especially for massively parallel computing architectures. Few attempts have been done, aimed at giving the possibility to explore architectural solutions, deriving information from extensive and reliable nanoarray characterization. Moreover, in the nanotechnology arena there is still not a clear winner, so it is important to be able to target different technologies, not to miss the next big thing. We present a tool, ToPoliNano, that enables such a multi-technological characterization in terms of logic behavior, power and timing performance, area and layout constraints, on the basis of specific technological and topological descriptions. This tool can aid the design process, beside providing a comprehensive simulation framework for DC and timing simulations, and detailed power analysis. Design and simulation results will be shown for nanoarray-based circuits. ToPoliNano is the first real design tool that tackles the top down design of a circuit based on emerging technologies.","PeriodicalId":287602,"journal":{"name":"2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128825315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits 三维堆叠集成电路零性能开销在线故障检测与诊断

2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2012-07-04 DOI: 10.1145/2765491.2765514

S. Safiruddin, M. Lefter, D. Borodin, G. Voicu, S. Cotofana

{"title":"Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits","authors":"S. Safiruddin, M. Lefter, D. Borodin, G. Voicu, S. Cotofana","doi":"10.1145/2765491.2765514","DOIUrl":"https://doi.org/10.1145/2765491.2765514","url":null,"abstract":"In this paper we present a zero-performance-overhead online fault detection and diagnosis scheme that exploits the vertical proximity of hardware inherent in 3D stacked integrated circuits (3D-SIC). We consider a 3D stacked processor executing independent instruction streams from different threads, on each die. We propose the vertical clustering of functionally identical computational blocks in order to enable the utilization of the 3D specific low-latency interlayer communication infrastructure. The clustering facilitates the parallel re-execution of instructions on idle units located in the proximity of the units which initially computed them and in this way creates the means for fault diagnosis and detection. We detail the control, interconnection communication infrastructure, instruction distribution, and results processing policies required for our scheme. To determine the effectiveness of the approach, we evaluate its performance in terms of diagnosis latency and percentage of verified operations on 3 to 8 core processors implemented on 3 to 8 tier 3D-SICs, respectively, by means of simulations. Our experiments indicate that the diagnosis latency ranges from 9 to 5 cycles, for 3 to 8 cores, respectively. For transient fault detection our simulations indicate that 86% to 94% of all executed instructions are verified, for 3 to 8 cores, respectively. When only one of the layers is protected against transient faults the number of verified operations increases to 94% to 99%, for the same simulation conditions. This suggests that, if certain conditions are fulfilled at design time, our approach can completely protect one instruction stream identified as being critical for the application. Our simulations clearly indicate that the proposed scheme has the potential to improve the 3D stacked integrated circuits dependability with no performance overhead and at the expense of little area overhead.","PeriodicalId":287602,"journal":{"name":"2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114617663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors 双栅硅纳米线晶体管规则逻辑片的工艺/设计协同优化

2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2012-07-04 DOI: 10.1145/2765491.2765503

Shashikanth Bobba, P. Gaillardon, Jian Zhang, M. D. Marchi, D. Sacchetto, Y. Leblebici, G. Micheli

引用次数: 17

Low-power design technique with ambipolar double gate devices 双极双栅极器件的低功耗设计技术

2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2012-07-04 DOI: 10.1145/2765491.2765495

K. Jabeur, I. O’Connor, D. Navarro, S. L. Beux

引用次数: 2

RRAM-based FPGA for “normally off, instantly on” applications 基于ram的FPGA用于“正常关闭，立即打开”的应用

2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2012-07-04 DOI: 10.1145/2765491.2765510

O. Turkyilmaz, S. Onkaraiah, M. Reyboz, F. Clermidy, Hraziia, C. Anghel, J. Portal, M. Bocquet

引用次数: 45

Spintronic Threshold Logic Array (STLA) - a compact, low leakage, non-volatile gate array architecture 自旋电子阈值逻辑阵列(STLA) -一个紧凑，低泄漏，非易失性门阵列架构

2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2012-07-04 DOI: 10.1145/2765491.2765525

N. Nukala, Niranjan S. Kulkarni, S. Vrudhula

{"title":"Spintronic Threshold Logic Array (STLA) - a compact, low leakage, non-volatile gate array architecture","authors":"N. Nukala, Niranjan S. Kulkarni, S. Vrudhula","doi":"10.1145/2765491.2765525","DOIUrl":"https://doi.org/10.1145/2765491.2765525","url":null,"abstract":"This paper describes a novel, first of its kind architecture for a threshold logic gate using conventional MOSFETs and an STT-MTJ (Spin Torque Transfer-Magnetic Tunnelling Junction) device. The resulting cell, called STL which is extremely compact can be programmed to realize a large number of threshold functions, many of which would require a multilevel network of conventional CMOS logic gates. Next, we describe a novel array architecture consisting of STL cells onto which complex logic networks can be mapped. The resulting array, called STLA has several advantages not available with conventional logic. This type of logic (1) is non-volatile, (2) is structurally regular and operates like DRAM, (3) is fully observable and controllable, (4) has zero standby power. These advantages are demonstrated by implementing a 16-bit carry look-ahead adder and compared with two optimized conventional FPGA implementations (Carry Look Ahead Adder and Ripple Carry Adder). The STLA has 12X lower transistor count (compared to CLA-FPGA) and 10X reduction (compared to RCA-FPGA) with comparable energy which will continue to reduce as the STT-MTJ device technology matures.","PeriodicalId":287602,"journal":{"name":"2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126972286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15