Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices

As planar MOSFETs is approaching its physical scaling limits, FinFET becomes one of the most promising alternative structure to keep on the industry scaling-down trend for future technology generations of 22 nm and beyond. In this paper, we propose a statistical model of Negative Bias Temperature Instability (NBTI) tailored for FinFET SRAM Arrays. The model build upon an extension of the reaction-diffusion theory such that it can cover the natural variations encountered in nanoscale MOSFET circuits. Dynamic NBTI stress on SRAM cells is modeled by using stochastic input signals. A mitigation technology for minimizing the NBTI aging is also demonstrated by taking advantage of the independent-gate FinFET device structure using threshold voltage adjustment. We evaluated the impact of our proposal on the RAM stability by means of SPICE simulations with the BSIM-IMGModel for 22nm FinFET devices. Our simulations conducted at an accelerated temperature 125°C for 108 seconds (~3 years) indicate that a Vth compensation of 0.2V can almost preserve the WRITE and HOLD stability of the fresh device even after 3 years, while for the READ stability the compensation mechanism is less effective. However, the READ Static Noise Margin (SNM) experiences an insignificant decrease over the 3 years time span in the presence of a Vth compensation, while without compensation it decreases by a x4 factor. Thus we can conclude that the proposed technique can improve the stability of SRAM array during its operational life, hence improve the performance and reliability of the system.