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2012 IEEE Workshop on Signal Processing Systems最新文献

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ACO-Based Deadlock-Aware Fully-Adaptive Routing in Network-on-Chip Systems 片上网络系统中基于aco的死锁感知全自适应路由
2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.14
Kuan-Yu Su, Hsien-Kai Hsin, En-Jui Chang, A. Wu
{"title":"ACO-Based Deadlock-Aware Fully-Adaptive Routing in Network-on-Chip Systems","authors":"Kuan-Yu Su, Hsien-Kai Hsin, En-Jui Chang, A. Wu","doi":"10.1109/SiPS.2012.14","DOIUrl":"https://doi.org/10.1109/SiPS.2012.14","url":null,"abstract":"Ant Colony Optimization (ACO) is a problem-solving technique inspired by the behavior of real-world ant colony. ACO-based routing also has high potential on balancing the traffic load in the domain of Network-on-Chip (NoC), where the performance is generally dominated by traffic distribution and routing. Since the pheromone in ACO provides both spatial and temporal network information, we find ACO-based routing suitable for reducing the probability of deadlock and its penalty. With the three schemes inspired by the behavior of ants and named as ACO-based Deadlock-Aware Routing (ACO-DAR), our simulation shows that the occurrence of deadlock can be greatly suppressed and the network performance also improves as a consequence. Moreover, ACO-DAR makes use of the existing hardware of the original ACO-based routing, so the area overhead is minor and ACO-DAR is thus cost-effective.","PeriodicalId":286060,"journal":{"name":"2012 IEEE Workshop on Signal Processing Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121233096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Multiresolution Gabor Feature Extraction for Real Time Applications 实时应用的多分辨率Gabor特征提取
2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.56
Yong Cheol Peter Cho, Nandhini Chandramoorthy, K. Irick, N. Vijaykrishnan
{"title":"Multiresolution Gabor Feature Extraction for Real Time Applications","authors":"Yong Cheol Peter Cho, Nandhini Chandramoorthy, K. Irick, N. Vijaykrishnan","doi":"10.1109/SiPS.2012.56","DOIUrl":"https://doi.org/10.1109/SiPS.2012.56","url":null,"abstract":"Multiresolution Gabor filters are used for feature extraction for a variety of applications. Most hardware implementations have focused on iterative mechanisms on fixed hardware for implementing the different levels of resolution. In contrast, we present a configurable architecture that enhances the resource utilization of the hardware fabric. Our results show that our implementation achieves real-time performance on 2048×1536 images and exhibits 6 times speed up over a GPU implementation. Further, our FPGA implementation achieves an energy-efficiency of processing 0.4 fps/W as compared to the GPU that achieves 0.036 fps/W.","PeriodicalId":286060,"journal":{"name":"2012 IEEE Workshop on Signal Processing Systems","volume":"320 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122704712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Energy-Efficient LDPC Decoders Based on Error-Resiliency 基于容错的LDPC节能解码器
2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.60
Eric P. Kim, Naresh R Shanbhag
{"title":"Energy-Efficient LDPC Decoders Based on Error-Resiliency","authors":"Eric P. Kim, Naresh R Shanbhag","doi":"10.1109/SiPS.2012.60","DOIUrl":"https://doi.org/10.1109/SiPS.2012.60","url":null,"abstract":"Low density parity check (LDPC) codes are used in various communication standards. However, LDPC decoders are complex and power hungry. In this paper, we present an energy-efficient LDPC decoder based on statistical error compensation (SEC). Three different size LDPC codes, (50,25), (800,400), and (1800,900) were implemented with 5 iterations/block. Circuit simulations in a commercial 45nm process show that the SEC based LDPC decoder can operate at a supply voltage up to 38% less than the nominal voltage and tolerate up to 30× more errors over an SNR range of 3dB to 8dB, while maintaining less than 3× degradation in BER. This is equivalent with energy savings of 45.7% compared to conventional LDPC decoders, and 33.2% compared to a sign bit protected LDPC decoder.","PeriodicalId":286060,"journal":{"name":"2012 IEEE Workshop on Signal Processing Systems","volume":"49 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122744902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder 一种Gbit/s FPGA卷积LDPC解码器的功率特性
2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.50
Si-Yun J. Li, T. Brandon, D. Elliott, V. Gaudet
{"title":"Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder","authors":"Si-Yun J. Li, T. Brandon, D. Elliott, V. Gaudet","doi":"10.1109/SiPS.2012.50","DOIUrl":"https://doi.org/10.1109/SiPS.2012.50","url":null,"abstract":"In this paper, we present an FPGA implementation of parallel-node low-density-parity-check convolution-code encoder and decoder. A 2.4 Gbit/s rate-1/2 (3, 6) LDPC convolutional-code encoder and decoder were implemented on an Alter a development and education board (DE4). Detailed power measurements of the FPGA board for various configurations of the design have been conducted to characterize the power consumption of the decoder module. For a Eb/N0 of 5 dB, the decoder with 9 processor cores (pipelined decoder iteration stages) has a bit-error-rate performance of 10-10 and achieves an energy-per-coded-bit of 1.683 nJ based on raw power measurement results. The increase in Eb/N0 can effectively reduce the decoder power and energy-per-coded-bit for configurations with 5 or more processor cores for Eb/N0 <; 5 dB. The incremental decoder power cost and incremental energy-per-coded-bit also hold a linearly decreasing trend for each additional processor core.","PeriodicalId":286060,"journal":{"name":"2012 IEEE Workshop on Signal Processing Systems","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117164037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
High-Speed Signal Reconstruction with Orthogonal Matching Pursuit via Matrix Inversion Bypass 基于矩阵反转旁路的正交匹配追踪高速信号重构
2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.26
Guoxian Huang, Lei Wang
{"title":"High-Speed Signal Reconstruction with Orthogonal Matching Pursuit via Matrix Inversion Bypass","authors":"Guoxian Huang, Lei Wang","doi":"10.1109/SiPS.2012.26","DOIUrl":"https://doi.org/10.1109/SiPS.2012.26","url":null,"abstract":"Compressive sensing (CS) is an emerging research area that has great significance to the design of resource-constrained cyber physical systems. Signal reconstruction in CS remains a challenge due to its high computational complexity, which limits the practical application of CS. In this paper, we propose an algorithmic transformation referred to as Matrix Inversion Bypass (MIB) to reduce the computational complexity of the Orthogonal Matching Pursuit(OMP) based CS reconstruction. The proposed algorithm naturally leads to a parallel architecture for high-speed dedicated hardware implementations. Furthermore, by applying the proposed MIB, the energy consumption of CS reconstruction can be reduced as well. This is vital to many cyber-physical systems that are powered by batteries or renewable energy sources. Simulation results demonstrate the advantages of the proposed technique over the conventional OMP algorithm.","PeriodicalId":286060,"journal":{"name":"2012 IEEE Workshop on Signal Processing Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121442828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Towards a Fast and Hardware Efficient Sub-MM Precision Ranging System 一种快速、硬件高效的亚毫米级精密测距系统
2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.20
Tuba Ayhan, Tom Redant, M. Verhelst, W. Dehaene
{"title":"Towards a Fast and Hardware Efficient Sub-MM Precision Ranging System","authors":"Tuba Ayhan, Tom Redant, M. Verhelst, W. Dehaene","doi":"10.1109/SiPS.2012.20","DOIUrl":"https://doi.org/10.1109/SiPS.2012.20","url":null,"abstract":"A sub-mm ranging system, which estimates the time of flight of a RF signal between two nodes using Time of Arrival (ToA) estimation, is possible according to maximum likelihood estimator simulations and theoretical bounds on ToA estimation. In this paper we propose a frequency domain based ToA estimator for an indoor ranging system which is broken into 3 computational steps towards an efficiently implementable estimator. Performance of this hardware efficient estimator is comparable with the maximum likelihood estimator's and it is computationally efficient. Complexity of the computational steps can be traded off against each other. Moreover, the implementation-aware estimator provides high flexibility on choosing between transmitted signal energy, computational cost and precision of the ranging algorithm. In this work, a simulation precision better than 1 mm is obtained for SNRs below 0 dB, by transmitting an OFDM (Orthogonal Frequency Division Multiplexing) like signal whose duration is 9 μs, with a 6 GHz bandwidth on a 60 GHz carrier.","PeriodicalId":286060,"journal":{"name":"2012 IEEE Workshop on Signal Processing Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128030224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Reduced Complexity On-chip IQ-Imbalance Self-Calibration 降低芯片上智商不平衡自校准的复杂性
2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.39
Chunshu Li, Min Li, S. Pollin, B. Debaillie, M. Verhelst, L. Perre, R. Lauwereins
{"title":"Reduced Complexity On-chip IQ-Imbalance Self-Calibration","authors":"Chunshu Li, Min Li, S. Pollin, B. Debaillie, M. Verhelst, L. Perre, R. Lauwereins","doi":"10.1109/SiPS.2012.39","DOIUrl":"https://doi.org/10.1109/SiPS.2012.39","url":null,"abstract":"The architectural simplicity of the direct-conversion scheme makes it an appealing architecture for low cost and low power transceivers. This architecture however demonstrates increased sensitivity to analog front-end impairments, such as gain and phase imbalance in the transceiver's in-phase and quadrature (IQ) paths. Especially when used in flexible software-defined radios, very fast, but low cost IQ-imbalance estimation and correction methods are required, to cope with the dynamically varying IQ imbalance due to environmental effect and frequency shifts. The main goal of this paper is to present an on-chip, off-line, extremely fast and low complexity self-calibration of IQ imbalance and carrier feed through for both the transmitter and receiver. Custom-designed training symbols allow to reduce the computational complexity, such that the calibration method can be performed at any user defined instance in negligible time. The reported complexity analysis shows that the whole calibration process takes up less than 4000 processor cycles, or 16us, when running on an OPENRISC 1200 core.","PeriodicalId":286060,"journal":{"name":"2012 IEEE Workshop on Signal Processing Systems","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133918984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Design of an ASIP LDPC Decoder Compliant with Digital Communication Standards 一种符合数字通信标准的ASIP LDPC解码器的设计
2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.62
B. Gal, C. Jégo
{"title":"Design of an ASIP LDPC Decoder Compliant with Digital Communication Standards","authors":"B. Gal, C. Jégo","doi":"10.1109/SiPS.2012.62","DOIUrl":"https://doi.org/10.1109/SiPS.2012.62","url":null,"abstract":"Application Specific Instruction set Processor (ASIP) is a promising approach to design an LDPC decoder that have to be compliant with multi-standards. Indeed, channel decoding is mainly dominated by dedicated hardware implementations that cannot easily support a large variety of digital communication standards. In this paper, an LDPC decoder architecture based on a publicly available MIPS processor core associated with a homogeneous matrix of processing units is presented. The proposed architecture corresponds to an intermediate approach between the creation of an new application specific instruction set processor and a fully dedicated decoder. The design and the FPGA prototyping of the resultant architectures are thus described. Results demonstrate the potential of this ASIP approach to implement efficient flexible LDPC decoders.","PeriodicalId":286060,"journal":{"name":"2012 IEEE Workshop on Signal Processing Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131004831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fusion of Multi-sensor Images Based on PCA and Self-Adaptive Regional Variance Estimation 基于PCA和自适应区域方差估计的多传感器图像融合
2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.42
Zhuozheng Wang, Yifan Wang, Ke-bin Jia, J. Deller
{"title":"Fusion of Multi-sensor Images Based on PCA and Self-Adaptive Regional Variance Estimation","authors":"Zhuozheng Wang, Yifan Wang, Ke-bin Jia, J. Deller","doi":"10.1109/SiPS.2012.42","DOIUrl":"https://doi.org/10.1109/SiPS.2012.42","url":null,"abstract":"An algorithm is presented for exploiting the properties of the lifting wavelet transform for multi-sensor image fusion. The method includes adaptive fusion arithmetic based on principal component analysis (PCA) and self-adaptive regional variance estimation. Characteristics of the wavelet coefficients are used to adaptively select fusion rules. A weighting method based on PCA is applied to low-frequency image components, and the regional variance estimation is applied to high-frequency components including edges and details of the original image. Experiments reveal that the methods are effective for multi-focus, visible-light, and infrared image fusion. Compared with traditional algorithms, the new algorithm not only improves the amount of preserved information and clarity, but also increases the correlation coefficient between the fused and source images.","PeriodicalId":286060,"journal":{"name":"2012 IEEE Workshop on Signal Processing Systems","volume":"1297 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113994865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Speech/Audio Signal Classification Using Spectral Flux Pattern Recognition 使用频谱通量模式识别的语音/音频信号分类
2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.36
Sangkil Lee, Jieun Kim, Insung Lee
{"title":"Speech/Audio Signal Classification Using Spectral Flux Pattern Recognition","authors":"Sangkil Lee, Jieun Kim, Insung Lee","doi":"10.1109/SiPS.2012.36","DOIUrl":"https://doi.org/10.1109/SiPS.2012.36","url":null,"abstract":"In this paper, we present a novel method for the improvement of speech and audio signal classification using spectral flux (SF) pattern recognition for the MPEG Unified Speech and Audio Coding (USAC) standard. For effective pattern recognition, the Gaussian mixture model (GMM)probability model is used. For the optimal GMM parameter extraction, we use the expectation maximization (EM)algorithm. The proposed classification algorithm is divided into two significant parts. The first one extracts the optimal parameters for the GMM. The second distinguishes between speech and audio signals using SF pattern recognition. The performance of the proposed classification algorithm shows better results compared to the conventionally implemented USAC scheme.","PeriodicalId":286060,"journal":{"name":"2012 IEEE Workshop on Signal Processing Systems","volume":"525 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116706154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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