Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems最新文献_第2页

Interrelations between Software Quality Metrics, Performance and Energy Consumption in Embedded Applications 嵌入式应用软件质量度量、性能和能耗之间的相互关系

Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems Pub Date : 2018-05-28 DOI: 10.1145/3207719.3207736

Lazaros Papadopoulos, C. Marantos, Georgios Digkas, Apostolos Ampatzoglou, A. Chatzigeorgiou, D. Soudris

{"title":"Interrelations between Software Quality Metrics, Performance and Energy Consumption in Embedded Applications","authors":"Lazaros Papadopoulos, C. Marantos, Georgios Digkas, Apostolos Ampatzoglou, A. Chatzigeorgiou, D. Soudris","doi":"10.1145/3207719.3207736","DOIUrl":"https://doi.org/10.1145/3207719.3207736","url":null,"abstract":"Source code refactorings and transformations are extensively used by embedded system developers to improve the quality of applications, often supported by various open source and proprietary tools. They either aim at improving the design time quality such as the maintainability and reusability of software artifacts, or the runtime quality such as performance and energy efficiency. However, an inherent trade-off between design- and run-time qualities is often present posing challenges to embedded software development. This work is a first step towards the investigation of the impact of transformations for improving the performance and the energy efficiency on software quality metrics and the impact of refactorings for increasing the design time quality on the execution time, the memory and the energy consumption. Based on a set of embedded applications from widely used benchmark suites and typical transformations and refactorings, we identify interrelations and trade-offs between the aforementioned metrics.","PeriodicalId":284835,"journal":{"name":"Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124295831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

Reinforcement Learning for Power-Efficient Grant Prediction in LTE LTE中能效授权预测的强化学习

Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems Pub Date : 2018-05-28 DOI: 10.1145/3207719.3207722

Peter Brand, J. Falk, Jonathan Ah Sue, J. Brendel, R. Hasholzner, Jürgen Teich

{"title":"Reinforcement Learning for Power-Efficient Grant Prediction in LTE","authors":"Peter Brand, J. Falk, Jonathan Ah Sue, J. Brendel, R. Hasholzner, Jürgen Teich","doi":"10.1145/3207719.3207722","DOIUrl":"https://doi.org/10.1145/3207719.3207722","url":null,"abstract":"Reducing the energy consumption of mobile phones is a major concern in the design of cellular modem solutions for LTE and 5G standards. Apart from optimizing hardware for power efficiency, dynamic power management, i.e., powering down idle system components, is a crucial means to achieve this goal. The techniques proposed so far, however, are reactive rather than proactive. This leads to the inability to exploit a significant amount of opportunities to power down components, as the opportunity is recognized too late. We propose a dynamic power management technique that is capable of exploiting said opportunities through the application of reinforcement learning prediction techniques for proactive power management. However, the additional computational effort for prediction algorithms must be carefully analyzed and taken into account. Therefore, we investigate which conditions have to be met in order to achieve net energy savings. The proposed technique has been implemented and evaluated for potential savings on simulated traces of LTE data. The resulting predictor is designed to be trained online, without any prior system knowledge. For a fair evaluation and comparison, the power consumption of the training phase is also considered in the analysis. It is shown that energy savings of up to 23.9 % may be obtained on a modem for scenarios such as HTTP streaming.","PeriodicalId":284835,"journal":{"name":"Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122334596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Mitigating Data Cache Aging through Compiler-Driven Memory Allocation 通过编译器驱动的内存分配减轻数据缓存老化

Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems Pub Date : 2018-05-28 DOI: 10.1145/3207719.3207731

Dominic Oehlert, Arno Luppold, H. Falk

引用次数: 2

Fast and Portable Vector DSP Simulation Through Automatic Vectorization 基于自动矢量化的快速便携式矢量DSP仿真

Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems Pub Date : 2018-05-28 DOI: 10.1145/3207719.3207720

J. Mundichipparakkal, M. Bamakhrama, Roel Jordans

引用次数: 0

stdcbench

Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems Pub Date : 2018-05-28 DOI: 10.1145/3207719.3207726

P. K. Krause

{"title":"stdcbench","authors":"P. K. Krause","doi":"10.1145/3207719.3207726","DOIUrl":"https://doi.org/10.1145/3207719.3207726","url":null,"abstract":"Benchmark programs are useful for measuring performance. Benchmarks written in C effectively benchmark the performance of a C implementation consisting of hardware, compiler and standard library. For small systems (i.e. systems with just a few KB of memory) three well-known and widely used benchmarks are Whetstone, Dhrystone and Coremark. However, all three have their shortcomings. Whetstone scores depend heavily on the performance of floating-point functions from the standard library. Dhrystone scores depend heavily on the performance of just a few string processing functions from the standard library. Coremark intentionally avoids using the standard library and the scores heavily depend on the performance of matrix multiplications. All three thus highly depend on a single aspect of the C implementation each, so that optimizations targeting that aspect have a huge effect on scores. stdcbench is a benchmark for small systems that tries to give a more balanced reflection of performance. It is intended to be usable for a wide range of C implementations for small systems. We present the design of stdcbench, and discuss a few benchmark results also in comparison to Dhrystone and Coremark.","PeriodicalId":284835,"journal":{"name":"Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114404356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems 第21届嵌入式系统软件与编译器国际研讨会论文集

Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems Pub Date : 2018-05-28 DOI: 10.1145/3207719

引用次数: 0

Automatic Optimization of Redundant Message Routings in Automotive Networks 汽车网络中冗余信息路由的自动优化

Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems Pub Date : 2018-05-28 DOI: 10.1145/3207719.3207725

Fedor Smirnov, Felix Reimann, J. Teich, Zhao Han, M. Glaß

{"title":"Automatic Optimization of Redundant Message Routings in Automotive Networks","authors":"Fedor Smirnov, Felix Reimann, J. Teich, Zhao Han, M. Glaß","doi":"10.1145/3207719.3207725","DOIUrl":"https://doi.org/10.1145/3207719.3207725","url":null,"abstract":"To cope with the strict reliability requirements of safety-critical ADAS applications, the upcoming TSN standard introduces mechanisms that enable transmission redundancy at any switch or end node. However, it is up to the designer to decide at which points and for which messages to activate transmission redundancy. This significantly increases the design space and requires to trade-off reliability with other routing-related design objectives like network load, transmission timing, or the monetary cost of the hardware. As a remedy, this paper a) presents two different exact approaches to generate feasible redundant message routings and b) proposes an extension of the state-of-the-art approach for the multi-objective routing optimization, enabling the optimizer to directly adjust system features that are relevant for the design objectives. A case study with an application from the automotive domain compares the optimization capabilities of the presented approaches for the routing generation and demonstrates the significant gain in optimization power that is achieved with the proposed optimization extension.","PeriodicalId":284835,"journal":{"name":"Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems","volume":"158 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128838848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Multi-Criteria Compiler-Based Optimization of Hard Real-Time Systems 基于多准则编译器的硬实时系统优化

Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems Pub Date : 2018-05-28 DOI: 10.1145/3207719.3207730

Kateryna Muts, Arno Luppold, H. Falk

引用次数: 7

Less is More: Exploiting the Standard Compiler Optimization Levels for Better Performance and Energy Consumption 少即是多:利用标准编译器优化水平，以获得更好的性能和能耗

Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems Pub Date : 2018-02-27 DOI: 10.1145/3207719.3207727

Kyriakos Georgiou, Craig Blackmore, S. X. D. Souza, K. Eder

{"title":"Less is More: Exploiting the Standard Compiler Optimization Levels for Better Performance and Energy Consumption","authors":"Kyriakos Georgiou, Craig Blackmore, S. X. D. Souza, K. Eder","doi":"10.1145/3207719.3207727","DOIUrl":"https://doi.org/10.1145/3207719.3207727","url":null,"abstract":"This paper presents the interesting observation that by performing fewer of the optimizations available in a standard compiler optimization level such as -02, while preserving their original ordering, significant savings can be achieved in both execution time and energy consumption. This observation has been validated on two embedded processors, namely the ARM Cortex-M0 and the ARM Cortex-M3, using two different versions of the LLVM compilation framework; v3.8 and v5.0. Experimental evaluation with 71 embedded benchmarks demonstrated performance gains for at least half of the benchmarks for both processors. An average execution time reduction of 2.4% and 5.3% was achieved across all the benchmarks for the Cortex-M0 and Cortex-M3 processors, respectively, with execution time improvements ranging from 1% up to 90% over the -02. The savings that can be achieved are in the same range as what can be achieved by the state-of-the-art compilation approaches that use iterative compilation or machine learning to select flags or to determine phase orderings that result in more efficient code. In contrast to these time consuming and expensive to apply techniques, our approach only needs to test a limited number of optimization configurations, less than 64, to obtain similar or even better savings. Furthermore, our approach can support multi-criteria optimization as it targets execution time, energy consumption and code size at the same time.","PeriodicalId":284835,"journal":{"name":"Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124166042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18