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Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)最新文献

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Low power implementation of a turbo-decoder on programmable architectures 涡轮解码器在可编程架构上的低功耗实现
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1145/370155.370425
F. Gilbert, A. Worm, N. Wehn
{"title":"Low power implementation of a turbo-decoder on programmable architectures","authors":"F. Gilbert, A. Worm, N. Wehn","doi":"10.1145/370155.370425","DOIUrl":"https://doi.org/10.1145/370155.370425","url":null,"abstract":"Low power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal architectures. Thus low power implementations of advanced channel decoding techniques are mandatory. In this paper we present a low power implementation of the most sophisticated channel decoding algorithm (turbo-decoding) on programmable architectures. Low power optimization is performed on two abstraction levels: on the system level by the use of an intelligent cancellation technique, and on the implementation level by the use of dynamic voltage scaling. With these techniques we can reduce the worst case energy consumption to 55% using data of state-of-the-art processors. Our approach is also applicable for hardware implementations. To the best of our knowledge, this is the first in-depth study of low power implementations of turbo-decoders based on voltage scheduling for third generation wireless systems.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125857522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
On-chip interconnections: impact of adjacent lines on timing 片上互连:相邻线路对时序的影响
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1109/ASPDAC.2001.913364
D. Deschacht, G. Servel
{"title":"On-chip interconnections: impact of adjacent lines on timing","authors":"D. Deschacht, G. Servel","doi":"10.1109/ASPDAC.2001.913364","DOIUrl":"https://doi.org/10.1109/ASPDAC.2001.913364","url":null,"abstract":"As CMOS technology scales down, the coupling capacitance between adjacent wires plays dominant part in wire load and interference becomes a serious problem for VLSI design. In this paper, we focus on delay increase caused by adjacent lines. This increase in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. We propose an analytical expression to compute the delay in the presence of coupling that takes explicitly into account interconnect resistance and capacitance, driver resistance and relative driver strengths.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129102310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores 片上系统外围核的跟踪驱动系统级功率评估
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1109/ASPDAC.2001.913324
T. Givargis, F. Vahid, J. Henkel
{"title":"Trace-driven system-level power evaluation of system-on-a-chip peripheral cores","authors":"T. Givargis, F. Vahid, J. Henkel","doi":"10.1109/ASPDAC.2001.913324","DOIUrl":"https://doi.org/10.1109/ASPDAC.2001.913324","url":null,"abstract":"Our earlier work for fast evaluation of power consumption of general cores in a system-on-a-chip described techniques that involved isolating high-level instructions of a core, measuring gate-level power consumption per instruction and then annotating a system-level simulation model with the obtained data. In this work, we describe a method for speeding up the evaluation further, through the use of instruction traces and trace simulators for every core, not just microprocessor cores. Our method shows noticeable speedups at an acceptable loss of accuracy. We show that reducing trace sizes can speed up the method even further. The speedups allow for more extensive system-level power exploration and hence better optimization.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126326122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
An 8-b nRERL microprocessor for ultra-low-energy applications 用于超低能耗应用的8-b nrel微处理器
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1145/370155.370242
Seokkee Kim, Jun-Ho Kwon, S. Chae
{"title":"An 8-b nRERL microprocessor for ultra-low-energy applications","authors":"Seokkee Kim, Jun-Ho Kwon, S. Chae","doi":"10.1145/370155.370242","DOIUrl":"https://doi.org/10.1145/370155.370242","url":null,"abstract":"We describe the design of an nRERL microprocessor for ultra-low-energy applications, nRERL (nMOS Reversible Energy Recovery Logic) is a new reversible adiabatic logic circuit using only nMOS transistors, which can be operated at the leakage-current level. We focus on two main issues; first, the design of a full adiabatic microprocessor, which uses only adiabatic components for all the functional blocks, second, the energy consumption of the nRERL microprocessor including its clocked power generator (CPG). With the experimental results, the nRERL microprocessor consumed 26.22 pJ at 440 kHz.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116586814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A pipelined ADC macro design for multiple applications 为多个应用设计的流水线ADC宏
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1109/ASPDAC.2001.913317
K. Tani, N. Nikai, A. Wada, T. Sawai
{"title":"A pipelined ADC macro design for multiple applications","authors":"K. Tani, N. Nikai, A. Wada, T. Sawai","doi":"10.1109/ASPDAC.2001.913317","DOIUrl":"https://doi.org/10.1109/ASPDAC.2001.913317","url":null,"abstract":"We present a new design methodology for high-speed analog-to-digital converter (ADC) macros based on our original pipelined 10-bit ADC. With library re-use methodology and performance driven optimization techniques, we have been able to both shorten the design period and to meet application specifications for items such as speed and power consumption. Using this method, we have developed ADC macros from 10-bit to 8-bit and 6-bit. They can be embedded into system LSIs for communication and multimedia applications.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124934967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers 使用等效检查器解决完全合成处理器核心的验证瓶颈
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1109/ASPDAC.2001.913300
G. SubashChandar, S. Vaideeswaran
{"title":"Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers","authors":"G. SubashChandar, S. Vaideeswaran","doi":"10.1109/ASPDAC.2001.913300","DOIUrl":"https://doi.org/10.1109/ASPDAC.2001.913300","url":null,"abstract":"Formal verification plays an important role in the verification of complex processors. In this paper, we discuss the usage and impact of equivalence checking in the verification of TI's TMS320C27X DSP core. During various phases of the design, we need to ensure the correctness of the design, a significant part of which could be best done with an equivalence checker. (For example, verifying the functionality of the netlist after CTS insertion with the one before CTS insertion). The capabilities and limitations of the commercial equivalence checkers are studied and a set of guidelines for their effective usage during different phases of the design is proposed. Also, a set of RTL coding guidelines to make the design equivalence checker friendly is detailed. Further, we discuss constrained mode equivalence checking which could be used if the implementation design is a super set of a reference design. The verification cycle time reduction and the salient features of an automated methodology that was developed specifically for our DSP core are described.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"427 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132907984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
VLSI block placement using less flexibility first principles VLSI块放置采用灵活性较低的第一原则
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1109/ASPDAC.2001.913374
Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu
{"title":"VLSI block placement using less flexibility first principles","authors":"Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu","doi":"10.1109/ASPDAC.2001.913374","DOIUrl":"https://doi.org/10.1109/ASPDAC.2001.913374","url":null,"abstract":"A deterministic algorithm for VLSI block placement was developed through human's accumulated experience in solving \"packing\" problem. Rectangle packing problem is just a simplified case of the polygon-shape stone plate packing problem that the ancient masons needed to face. Several \"packing\" principles derived from the so-called \"less flexibility first\" experience of the masons. A k-d tree data structure is used for manipulating the packed rectangles under the derived packing principles. Experiment results demonstrate that the algorithm is effective and promising in building block layout application.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133280633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Efficient global fanout optimization algorithms 高效的全局扇出优化算法
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1109/ASPDAC.2001.913369
R. Murgai
{"title":"Efficient global fanout optimization algorithms","authors":"R. Murgai","doi":"10.1109/ASPDAC.2001.913369","DOIUrl":"https://doi.org/10.1109/ASPDAC.2001.913369","url":null,"abstract":"Fanout optimization is a fundamental problem in timing optimization. Most of the research has focussed on the fanout optimization problem for a single net (or the local fanout optimization problem-LFO). The real goal, however, is to optimize the delay through the entire circuit by fanout optimization incurring minimum area penalty and without violating the pin loading constraints. This is known as the global fanout optimization (GFO) problem. In this paper, we show that the techniques proposed so far in the literature are either impractical or ineffective for large designs. We propose simple yet efficient and effective schemes for GFO and show that they outperform the \"nearly-optimum\" reverse topological (RT) algorithm on large industrial designs. One of these schemes yields only 0.3% worse circuit delay on average, but incurs only 18.5% of the area penalty as compared to the RT algorithm and is about 3 times faster. A popularly used mincut-based strategy was not found to be effective.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"664 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132234869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel network node architecture for high performance and function flexibility 一种具有高性能和功能灵活性的新型网络节点架构
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1109/ASPDAC.2001.913366
T. Murooka, A. Takahara, T. Miyazaki
{"title":"A novel network node architecture for high performance and function flexibility","authors":"T. Murooka, A. Takahara, T. Miyazaki","doi":"10.1109/ASPDAC.2001.913366","DOIUrl":"https://doi.org/10.1109/ASPDAC.2001.913366","url":null,"abstract":"We developed a flexible network node that is tuned for high-speed and multilayer packet manipulation. The key idea is a dynamic function assignment mechanism; each packet processing task is assigned to several processing modules in an on-the-fly manner and incoming packets are processed in them. With this mechanism, we can freely arrange the modules and add extra ones if more processing power is needed. In addition, the processing modules are realized using field programmable gate arrays (FPGAs) and microprocessing units (MPUs). Thus, the functionality of each module can be dynamically changed at any time. In this paper, the system concept and its implementation are described with an example application.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134360618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A dynamically phase adjusting PLL with a variable delay 具有可变延迟的动态相位调节锁相环
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1109/ASPDAC.2001.913318
T. Yasuda, H. Fujita, H. Onodera
{"title":"A dynamically phase adjusting PLL with a variable delay","authors":"T. Yasuda, H. Fujita, H. Onodera","doi":"10.1109/ASPDAC.2001.913318","DOIUrl":"https://doi.org/10.1109/ASPDAC.2001.913318","url":null,"abstract":"Phase locked loops (PLLs) are widely used for many purposes. The lock-up performance is one of the most important target items in designing PLLs. In a digital PLL, it is difficult to control the frequency and phase independently, which makes it difficult to improve lock-up performance. A variable delay circuit which adjusts only the phase of the PLL is introduced here. A full loop model simulation with measured controllable delay shows the effectiveness of applying the phase adjust method with the variable delay to the PLL.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134385052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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