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Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)最新文献

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Efficient minimum spanning tree construction without Delaunay triangulation [VLSI CAD] 无Delaunay三角剖分的高效最小生成树构建[VLSI CAD]
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1145/370155.370320
H. Zhou, Narendra V. Shenoy, W. Nicholls
{"title":"Efficient minimum spanning tree construction without Delaunay triangulation [VLSI CAD]","authors":"H. Zhou, Narendra V. Shenoy, W. Nicholls","doi":"10.1145/370155.370320","DOIUrl":"https://doi.org/10.1145/370155.370320","url":null,"abstract":"Minimum spanning tree problem is a very important problem in VLSI CAD. Given n points in a plane, a minimum spanning tree is a set of edges which connects all the points and has a minimum total length. A naive approach enumerates edges on all pairs of points and takes at least /spl Omega/(n/sup 2/) time. More efficient approaches find a minimum spanning tree only among edges in the Delaunay triangulation of the points. However, Delaunay triangulation is not well defined in rectilinear distance. In this paper, we first establish a framework for minimum spanning tree construction which is based on a general concept of spanning graphs. A spanning graph is a natural definition and not necessarily a Delaunay triangulation. Based on this framework, we then design an O(nlogn) sweep-line algorithm to construct a rectilinear minimum spanning tree without using Delaunay triangulation.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123079198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
An on-chip 96.5% current efficiency CMOS linear regulator 片上96.5%电流效率的CMOS线性稳压器
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1109/ASPDAC.2001.913322
K. Sunaga, T. Endoh, H. Sakuraba, F. Masuoka
{"title":"An on-chip 96.5% current efficiency CMOS linear regulator","authors":"K. Sunaga, T. Endoh, H. Sakuraba, F. Masuoka","doi":"10.1109/ASPDAC.2001.913322","DOIUrl":"https://doi.org/10.1109/ASPDAC.2001.913322","url":null,"abstract":"A proposed linear regulator uses a flexible control technique of output current (FCOC) to achieve 96.5% efficiency. The FCOC technique drives a flexible output current according to the output current variation and stable output voltage supply. The linear regulator fabricated by 1.2 /spl mu/m CMOS process occupies 0.423 mm/sup 2/. The fabricated linear regulator achieves 96.5% current efficiency and less than 6.81 mVpp output voltage fluctuation at an output current frequency from 1.8 Hz to 100 MHz.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121117679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures SoC设计与异构多处理器目标架构的可扩展和灵活的协同仿真
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1145/370155.370276
P. Gerin, S. Yoo, G. Nicolescu, A. Jerraya
{"title":"Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures","authors":"P. Gerin, S. Yoo, G. Nicolescu, A. Jerraya","doi":"10.1145/370155.370276","DOIUrl":"https://doi.org/10.1145/370155.370276","url":null,"abstract":"In this paper, we present a cosimulation environment that provides modularity, scalability, and flexibility in cosimulation of SoC designs with heterogeneous multi-processor target architectures. Our cosimulation environment is based on an object-oriented simulation environment, SystemC. Exploiting the object orientation in SystemC representation, we achieve modularity and scalability of cosimulation by developing modular cosimulation interfaces. The object orientation also enables mixed-level cosimulation to be easily implemented; thereby the designer can have flexibility in trade off between simulation performance and accuracy. Experiments with an IS-95 CDMA cellular phone system design show the effectiveness of the cosimulation environment.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125193998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
LEneS: task scheduling for low-energy systems using variable supply voltage processors LEneS:使用可变电源电压处理器的低能耗系统的任务调度
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1145/370155.370511
F. Gruian, K. Kuchcinski
{"title":"LEneS: task scheduling for low-energy systems using variable supply voltage processors","authors":"F. Gruian, K. Kuchcinski","doi":"10.1145/370155.370511","DOIUrl":"https://doi.org/10.1145/370155.370511","url":null,"abstract":"The work presented in this paper addresses minimization of the energy consumption of a system during system-level design. The paper focuses on scheduling techniques for architectures containing variable supply voltage processors, running dependent tasks. We introduce our new approach for low-energy scheduling (LEneS) and compare it to two other scheduling methods. LEneS is based on a list-scheduling heuristic with dynamic recalculation of priorities, and assumes a given allocation and assignment of tasks to processors. Our approach minimizes the energy by choosing the best combination of supply voltages for each task running on its processor. The set of experiments we present shows that, using the LEneS approach, we can achieve up to 28% energy savings for the tightest deadlines, and up to 77% energy savings when these deadlines are relaxed by 50%.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115084648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 202
Processor-programmable memory BIST for bus-connected embedded memories 处理器可编程存储器，用于总线连接的嵌入式存储器
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1109/ASPDAC.2001.913327
Ching-Hong Tsai, Cheng-Wen Wu
{"title":"Processor-programmable memory BIST for bus-connected embedded memories","authors":"Ching-Hong Tsai, Cheng-Wen Wu","doi":"10.1109/ASPDAC.2001.913327","DOIUrl":"https://doi.org/10.1109/ASPDAC.2001.913327","url":null,"abstract":"We present a processor-programmable built-in self-test (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circuit can be programmed via an on chip microprocessor. Upon receiving the commands from the microprocessor, the BIST circuit generates pre-defined test patterns and compares the memory outputs with the expected outputs. Most popular memory test algorithms can be realized by properly programming the BIST circuit using the processor instructions. Compared with processor-based memory BIST schemes that use an assembly-language program to generate test patterns and compare the memory outputs, the test time of the proposed memory BIST scheme is greatly reduced.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116821735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
An optimum fitting algorithm for generation of reduced-order models 一种生成降阶模型的优化拟合算法
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1109/ASPDAC.2001.913306
M. Gourary, S. Rusakov, S. Ulyanov, M. Zharov, B. Mulvaney
{"title":"An optimum fitting algorithm for generation of reduced-order models","authors":"M. Gourary, S. Rusakov, S. Ulyanov, M. Zharov, B. Mulvaney","doi":"10.1109/ASPDAC.2001.913306","DOIUrl":"https://doi.org/10.1109/ASPDAC.2001.913306","url":null,"abstract":"The paper presents a new approach to the problem of automatic order reducing of a rational transfer function (TF). The approach is directed to obtain low-order models under criterion of minimal integral square error. The developed computational scheme allows one to determine the reduced model of the minimal order with a given error tolerance.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126442605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Power optimization and management in embedded systems 嵌入式系统中的电源优化与管理
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1109/ASPDAC.2001.913312
Massoud Pedram
{"title":"Power optimization and management in embedded systems","authors":"Massoud Pedram","doi":"10.1109/ASPDAC.2001.913312","DOIUrl":"https://doi.org/10.1109/ASPDAC.2001.913312","url":null,"abstract":"Power-efficient design requires reducing power dissipation in all parts of the design and during all stages of the design process subject to constraints on the system performance and quality of service (QoS). Power-aware high-level language compilers, dynamic power management policies, memory management schemes, bus encoding techniques, and hardware design tools are needed to meet these often-conflicting design requirements. This paper reviews techniques and tools for power-efficient embedded system design, considering the hardware platform, the application software, and the system software. Design examples from an Intel StrongARM based system are provided to illustrate the concepts and the techniques. This paper is not intended as a comprehensive review, rather as a starting point for understanding power-aware design methodologies and techniques targeted toward embedded systems.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115926699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 77
Multi-hit time-to-digital converter VLSI for high-energy physics experiments 用于高能物理实验的多命中时间-数字转换器VLSI
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1109/ASPDAC.2001.913261
Y. Arai
{"title":"Multi-hit time-to-digital converter VLSI for high-energy physics experiments","authors":"Y. Arai","doi":"10.1109/ASPDAC.2001.913261","DOIUrl":"https://doi.org/10.1109/ASPDAC.2001.913261","url":null,"abstract":"A multi-hit time-to-digital converter VLSI has been developed using a CMOS 0.3 /spl mu/m gate-array technology. The chip is designed for use in a high-energy physics experiment ATLAS. Precise timing signals are generated from 16 taps of an asymmetric ring oscillator oscillating at 80 MHz and controlled by a PLL circuit. A prototype chip has been developed, and a time resolution of 300 ps RMS was obtained. Many macro cells are developed to achieve such high resolution still using commercial gate-array technology.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132561206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Cell selection from technology libraries for minimizing power 电池选择从技术库，以尽量减少功率
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1109/ASPDAC.2001.913376
Yumin Zhang, X. Hu, D. Chen
{"title":"Cell selection from technology libraries for minimizing power","authors":"Yumin Zhang, X. Hu, D. Chen","doi":"10.1109/ASPDAC.2001.913376","DOIUrl":"https://doi.org/10.1109/ASPDAC.2001.913376","url":null,"abstract":"In this paper we present a new library-oriented cell selection approach to minimize power consumption of combinational circuits. Our unified mixed integer-linear-programming (MILP) formulation selects library cells with different gate sizes, supply voltages and threshold voltages simultaneously during technology mapping. Experimental results on benchmarks mapped to an industrial library show that our technique achieves 19% more power saving in less CPU time comparing with other approaches.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129402644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A higher level system communication model for object-oriented specification and design of embedded systems 面向对象的嵌入式系统规范与设计的高级系统通信模型
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455) Pub Date : 2001-01-30 DOI: 10.1109/ASPDAC.2001.913283
K. Svarstad, N. Ben-Fredj, G. Nicolescu, A. Jerraya
{"title":"A higher level system communication model for object-oriented specification and design of embedded systems","authors":"K. Svarstad, N. Ben-Fredj, G. Nicolescu, A. Jerraya","doi":"10.1109/ASPDAC.2001.913283","DOIUrl":"https://doi.org/10.1109/ASPDAC.2001.913283","url":null,"abstract":"The design starting point for current embedded systems design is getting higher and higher on the abstraction level scale in order to meet the challenge of the increasing design gap. Up to now the state-of-the-art tools and methods have used as a highest abstraction of communication for the send-receive over a channel, e.g. as in SDL and COSSAP. We introduce a novel higher level communication mechanism for system-level specification which has features supporting object-oriented descriptions and client-server type communication modelling as in CORBA. The communication primitives have been implemented as extensions to System-C, and simulation experiments have been performed.","PeriodicalId":281722,"journal":{"name":"Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114501304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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